LM3S3749 Datasheet, PDF (390/898 Pages) Texas Instruments – Stellaris® LM3S3749 Microcontroller

General-Purpose Input/Outputs (GPIOs)
Register 15: GPIO Pull-Up Select (GPIOPUR), offset 0x510
The GPIOPUR register is the pull-up control register. When a bit is set to 1, it enables a weak pull-up
resistor on the corresponding GPIO signal. Setting a bit in GPIOPUR automatically clears the
corresponding bit in the GPIO Pull-Down Select (GPIOPDR) register (see page 392). Write access
to this register is protected with the GPIOCR register. Bits in GPIOCR that are set to 0 will prevent
writes to the equivalent bit in this register.
Note:
The GPIO commit control registers provide a layer of protection against accidental
programming of critical hardware peripherals. Protection is currently provided for the NMI
pin (PB7) and the four JTAG/SWD pins (PC[3:0]). Writes to protected bits of the GPIO
Alternate Function Select (GPIOAFSEL) register (see page 384), GPIO Pull-Up Select
(GPIOPUR) register (see page 390), and GPIO Digital Enable (GPIODEN) register (see
page 394) are not committed to storage unless the GPIO Lock (GPIOLOCK) register (see
page 396) has been unlocked and the appropriate bits of the GPIO Commit (GPIOCR)
register (see page 397) have been set to 1.
GPIO Pull-Up Select (GPIOPUR)
GPIO Port A (APB) base: 0x4000.4000
GPIO Port A (AHB) base: 0x4005.8000
GPIO Port B (APB) base: 0x4000.5000
GPIO Port B (AHB) base: 0x4005.9000
GPIO Port C (APB) base: 0x4000.6000
GPIO Port C (AHB) base: 0x4005.A000
GPIO Port D (APB) base: 0x4000.7000
GPIO Port D (AHB) base: 0x4005.B000
GPIO Port E (APB) base: 0x4002.4000
GPIO Port E (AHB) base: 0x4005.C000
GPIO Port F (APB) base: 0x4002.5000
GPIO Port F (AHB) base: 0x4005.D000
GPIO Port G (APB) base: 0x4002.6000
GPIO Port G (AHB) base: 0x4005.E000
GPIO Port H (APB) base: 0x4002.7000
GPIO Port H (AHB) base: 0x4005.F000
Offset 0x510
Type R/W, reset -
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
PUE
Type RO
RO
RO
RO
RO
RO
RO
RO
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
-
-
-
-
-
-
-
-
Bit/Field
31:8
Name
reserved
Type
RO
Reset
0x00
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
390
November 17, 2011
Texas Instruments-Production Data