LM3S3749 Datasheet, PDF (22/898 Pages) Texas Instruments – Stellaris® LM3S3749 Microcontroller

Table of Contents
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Watchdog Peripheral Identification 0 (WDTPeriphID0), offset 0xFE0 ................................. 463
Watchdog Peripheral Identification 1 (WDTPeriphID1), offset 0xFE4 ................................. 464
Watchdog Peripheral Identification 2 (WDTPeriphID2), offset 0xFE8 ................................. 465
Watchdog Peripheral Identification 3 (WDTPeriphID3), offset 0xFEC ................................. 466
Watchdog PrimeCell Identification 0 (WDTPCellID0), offset 0xFF0 .................................... 467
Watchdog PrimeCell Identification 1 (WDTPCellID1), offset 0xFF4 .................................... 468
Watchdog PrimeCell Identification 2 (WDTPCellID2), offset 0xFF8 .................................... 469
Watchdog PrimeCell Identification 3 (WDTPCellID3 ), offset 0xFFC .................................. 470
Analog-to-Digital Converter (ADC) ............................................................................................. 471
Register 1: ADC Active Sample Sequencer (ADCACTSS), offset 0x000 ............................................. 481
Register 2: ADC Raw Interrupt Status (ADCRIS), offset 0x004 ........................................................... 482
Register 3: ADC Interrupt Mask (ADCIM), offset 0x008 ..................................................................... 483
Register 4: ADC Interrupt Status and Clear (ADCISC), offset 0x00C .................................................. 484
Register 5: ADC Overflow Status (ADCOSTAT), offset 0x010 ............................................................ 485
Register 6: ADC Event Multiplexer Select (ADCEMUX), offset 0x014 ................................................. 486
Register 7: ADC Underflow Status (ADCUSTAT), offset 0x018 ........................................................... 490
Register 8: ADC Sample Sequencer Priority (ADCSSPRI), offset 0x020 ............................................. 491
Register 9: ADC Processor Sample Sequence Initiate (ADCPSSI), offset 0x028 ................................. 493
Register 10: ADC Sample Averaging Control (ADCSAC), offset 0x030 ................................................. 494
Register 11: ADC Sample Sequence Input Multiplexer Select 0 (ADCSSMUX0), offset 0x040 ............... 495
Register 12: ADC Sample Sequence Control 0 (ADCSSCTL0), offset 0x044 ........................................ 497
Register 13: ADC Sample Sequence Result FIFO 0 (ADCSSFIFO0), offset 0x048 ................................ 500
Register 14: ADC Sample Sequence Result FIFO 1 (ADCSSFIFO1), offset 0x068 ................................ 500
Register 15: ADC Sample Sequence Result FIFO 2 (ADCSSFIFO2), offset 0x088 ................................ 500
Register 16: ADC Sample Sequence Result FIFO 3 (ADCSSFIFO3), offset 0x0A8 ............................... 500
Register 17: ADC Sample Sequence FIFO 0 Status (ADCSSFSTAT0), offset 0x04C ............................. 501
Register 18: ADC Sample Sequence FIFO 1 Status (ADCSSFSTAT1), offset 0x06C ............................. 501
Register 19: ADC Sample Sequence FIFO 2 Status (ADCSSFSTAT2), offset 0x08C ............................ 501
Register 20: ADC Sample Sequence FIFO 3 Status (ADCSSFSTAT3), offset 0x0AC ............................ 501
Register 21: ADC Sample Sequence Input Multiplexer Select 1 (ADCSSMUX1), offset 0x060 ............... 502
Register 22: ADC Sample Sequence Input Multiplexer Select 2 (ADCSSMUX2), offset 0x080 ............... 502
Register 23: ADC Sample Sequence Control 1 (ADCSSCTL1), offset 0x064 ........................................ 503
Register 24: ADC Sample Sequence Control 2 (ADCSSCTL2), offset 0x084 ........................................ 503
Register 25: ADC Sample Sequence Input Multiplexer Select 3 (ADCSSMUX3), offset 0x0A0 ............... 505
Register 26: ADC Sample Sequence Control 3 (ADCSSCTL3), offset 0x0A4 ........................................ 506
Universal Asynchronous Receivers/Transmitters (UARTs) ..................................................... 507
Register 1: UART Data (UARTDR), offset 0x000 ............................................................................... 517
Register 2: UART Receive Status/Error Clear (UARTRSR/UARTECR), offset 0x004 ........................... 519
Register 3: UART Flag (UARTFR), offset 0x018 ................................................................................ 521
Register 4: UART IrDA Low-Power Register (UARTILPR), offset 0x020 ............................................. 523
Register 5: UART Integer Baud-Rate Divisor (UARTIBRD), offset 0x024 ............................................ 524
Register 6: UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028 ....................................... 525
Register 7: UART Line Control (UARTLCRH), offset 0x02C ............................................................... 526
Register 8: UART Control (UARTCTL), offset 0x030 ......................................................................... 528
Register 9: UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034 ........................................... 530
Register 10: UART Interrupt Mask (UARTIM), offset 0x038 ................................................................. 532
Register 11: UART Raw Interrupt Status (UARTRIS), offset 0x03C ...................................................... 534
Register 12: UART Masked Interrupt Status (UARTMIS), offset 0x040 ................................................. 535
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November 17, 2011
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