LM3S6G11 Datasheet, PDF (802/827 Pages) Texas Instruments – Stellaris® LM3S6G11 Microcontroller

OBSOLETE: TI has discontinued production of this device.
Register Quick Reference
31
30
29
28
27
26
25
24
23
22
21
15
14
13
12
11
10
9
8
7
6
5
FMPRE5, type R/W, offset 0x214, reset 0xFFFF.FFFF
READ_ENABLE
READ_ENABLE
FMPRE6, type R/W, offset 0x218, reset 0x0000.0000
READ_ENABLE
READ_ENABLE
FMPRE7, type R/W, offset 0x21C, reset 0x0000.0000
READ_ENABLE
READ_ENABLE
FMPPE1, type R/W, offset 0x404, reset 0xFFFF.FFFF
PROG_ENABLE
PROG_ENABLE
FMPPE2, type R/W, offset 0x408, reset 0xFFFF.FFFF
PROG_ENABLE
PROG_ENABLE
FMPPE3, type R/W, offset 0x40C, reset 0xFFFF.FFFF
PROG_ENABLE
PROG_ENABLE
FMPPE4, type R/W, offset 0x410, reset 0xFFFF.FFFF
PROG_ENABLE
PROG_ENABLE
FMPPE5, type R/W, offset 0x414, reset 0xFFFF.FFFF
PROG_ENABLE
PROG_ENABLE
FMPPE6, type R/W, offset 0x418, reset 0x0000.0000
PROG_ENABLE
PROG_ENABLE
FMPPE7, type R/W, offset 0x41C, reset 0x0000.0000
PROG_ENABLE
PROG_ENABLE
Micro Direct Memory Access (μDMA)
μDMA Channel Control Structure (Offset from Channel Control Table Base)
Base n/a
DMASRCENDP, type R/W, offset 0x000, reset -
ADDR
ADDR
DMADSTENDP, type R/W, offset 0x004, reset -
ADDR
ADDR
DMACHCTL, type R/W, offset 0x008, reset -
DSTINC
ARBSIZE
DSTSIZE
SRCINC
SRCSIZE
XFERSIZE
Micro Direct Memory Access (μDMA)
μDMA Registers (Offset from μDMA Base Address)
Base 0x400F.F000
DMASTAT, type RO, offset 0x000, reset 0x001F.0000
DMACFG, type WO, offset 0x004, reset -
STATE
20
19
18
17
16
4
3
2
1
0
NXTUSEBURST
ARBSIZE
XFERMODE
DMACHANS
MASTEN
MASTEN
802
July 24, 2012
Texas Instruments-Production Data