LM3S6G11 Datasheet, PDF (659/827 Pages) Texas Instruments – Stellaris® LM3S6G11 Microcontroller

OBSOLETE: TI has discontinued production of this device.
Stellaris^® LM3S6G11 Microcontroller
15.1
Block Diagram
As shown in Figure 15-1 on page 659, the Ethernet Controller is functionally divided into two layers:
the Media Access Controller (MAC) layer and the Network Physical (PHY) layer. These layers
correspond to the OSI model layers 2 and 1, respectively. The CPU accesses the Ethernet Controller
via the MAC layer. The MAC layer provides transmit and receive processing for Ethernet frames.
The MAC layer also provides the interface to the PHY layer via an internal Media Independent
Interface (MII). The PHY layer communicates with the Ethernet bus.
Figure 15-1. Ethernet Controller
ARM Cortex M3
EMtehdeiranet ConPtrhoyllseircal
Access Layer Entity
Controller
MAC
(Layer 2)
PHY
(Layer 1)
Magnetics
RJ45
Figure 15-2 on page 659 shows more detail of the internal structure of the Ethernet Controller and
how the register set relates to various functions.
Figure 15-2. Ethernet Controller Block Diagram
Interrupt
Interrupt
Control
MACRIS
MACIACK
MACIM
Individual
Address
MACIA0
MACIA1
Receive
Control
MACRCTL
MACNP
Data
Access
MACDDATA
Transmit
Control
MACTCTL
MACTHR
MACTR
MII
Control
MACMCTL
MACMDV
MACMTXD
MACMRXD
MDIX
MAC LED
MACLED
Transmit
FIFO
Receive
FIFO
Transmit
Encoding
Pulse
Shaping
Collision
Detect
Carrier
Sense
Receive
Decoding
Clock
Recovery
TXOP
TXON
MDIX
RXIP
RXIN
Media Independent Interface
Management Register Set
MR0
MR3
MR6
MR27
MR31
MR1
MR4
MR16
MR29
MR2
MR5
MR17
MR30
Auto
Negotiation
Clock
Reference
XTALPPHY
XTALNPHY
LED0
LED1
July 24, 2012
659
Texas Instruments-Production Data