LM3S6G11 Datasheet, PDF (121/827 Pages) Texas Instruments – Stellaris® LM3S6G11 Microcontroller

OBSOLETE: TI has discontinued production of this device.
Stellaris^® LM3S6G11 Microcontroller
Register 31: Interrupt Control and State (INTCTRL), offset 0xD04
Note: This register can only be accessed from privileged mode.
The INCTRL register provides a set-pending bit for the NMI exception, and set-pending and
clear-pending bits for the PendSV and SysTick exceptions. In addition, bits in this register indicate
the exception number of the exception being processed, whether there are preempted active
exceptions, the exception number of the highest priority pending exception, and whether any interrupts
are pending.
When writing to INCTRL, the effect is unpredictable when writing a 1 to both the PENDSV and
UNPENDSV bits, or writing a 1 to both the PENDSTSET and PENDSTCLR bits.
Interrupt Control and State (INTCTRL)
Base 0xE000.E000
Offset 0xD04
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
NMISET
reserved
PENDSV UNPENDSV PENDSTSET PENDSTCLR reserved ISRPRE ISRPEND
Type R/W
RO
RO
R/W
WO
R/W
WO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
VECPEND
RETBASE
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
20
19
reserved
RO
RO
0
0
4
3
VECACT
RO
RO
0
0
18
17
16
VECPEND
RO
RO
RO
0
0
0
2
1
0
RO
RO
RO
0
0
0
Bit/Field
31
30:29
28
Name
NMISET
reserved
PENDSV
Type
R/W
RO
R/W
Reset
0
0x0
0
Description
NMI Set Pending
Value Description
0 On a read, indicates an NMI exception is not pending.
On a write, no effect.
1 On a read, indicates an NMI exception is pending.
On a write, changes the NMI exception state to pending.
Because NMI is the highest-priority exception, normally the processor
enters the NMI exception handler as soon as it registers the setting of
this bit, and clears this bit on entering the interrupt handler. A read of
this bit by the NMI exception handler returns 1 only if the NMI signal is
reasserted while the processor is executing that handler.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
PendSV Set Pending
Value Description
0 On a read, indicates a PendSV exception is not pending.
On a write, no effect.
1 On a read, indicates a PendSV exception is pending.
On a write, changes the PendSV exception state to pending.
Setting this bit is the only way to set the PendSV exception state to
pending. This bit is cleared by writing a 1 to the UNPENDSV bit.
July 24, 2012
121
Texas Instruments-Production Data