LM3S6G11 Datasheet, PDF (755/827 Pages) Texas Instruments – Stellaris® LM3S6G11 Microcontroller

OBSOLETE: TI has discontinued production of this device.
Stellaris^® LM3S6G11 Microcontroller
Table 18-7. Signals by Pin Number (continued)
Pin Number
Pin Name
Pin Type Buffer Type^a Description
F12
GND
-
Power Ground reference for logic and I/O pins.
PD0
I/O
TTL
GPIO port D bit 0.
CCP6
I/O
TTL
Capture/Compare/PWM 6.
G1
U1Rx
I
TTL
UART module 1 receive. When in IrDA mode, this signal has IrDA
modulation.
U2Rx
I
TTL
UART module 2 receive. When in IrDA mode, this signal has IrDA
modulation.
PD1
I/O
TTL
GPIO port D bit 1.
CCP2
I/O
TTL
Capture/Compare/PWM 2.
CCP7
I/O
TTL
Capture/Compare/PWM 7.
G2
U1Tx
O
TTL
UART module 1 transmit. When in IrDA mode, this signal has IrDA
modulation.
U2Tx
O
TTL
UART module 2 transmit. When in IrDA mode, this signal has IrDA
modulation.
VDDC
G3
-
Power Positive supply for most of the logic function, including the
processor core and most peripherals. The voltage on this pin is
1.3 V and is supplied by the on-chip LDO. The VDDC pins should
only be connected to the LDO pin and an external capacitor as
specified in Table 20-6 on page 779 .
G10
VDD
-
Power Positive supply for I/O and some logic.
G11
VDD
-
Power Positive supply for I/O and some logic.
G12
VDD
-
Power Positive supply for I/O and some logic.
PD3
I/O
TTL
GPIO port D bit 3.
CCP0
I/O
TTL
Capture/Compare/PWM 0.
H1
CCP7
I/O
TTL
Capture/Compare/PWM 7.
U1Tx
O
TTL
UART module 1 transmit. When in IrDA mode, this signal has IrDA
modulation.
PD2
I/O
TTL
GPIO port D bit 2.
CCP5
I/O
TTL
Capture/Compare/PWM 5.
H2
CCP6
I/O
TTL
Capture/Compare/PWM 6.
U1Rx
I
TTL
UART module 1 receive. When in IrDA mode, this signal has IrDA
modulation.
H3
GND
-
Power Ground reference for logic and I/O pins.
H10
VDD
-
Power Positive supply for I/O and some logic.
H11
RST
I
TTL
System reset input.
PF1
H12
CCP3
I/O
TTL
GPIO port F bit 1.
I/O
TTL
Capture/Compare/PWM 3.
XTALNPHY
O
Analog Ethernet PHY XTALN 25-MHz oscillator crystal output. Leave this
J1
pin unconnected when using a single-ended 25-MHz clock input
connected to the XTALPPHY pin.
J2
XTALPPHY
I
Analog Ethernet PHY XTALP 25-MHz oscillator crystal input or external
clock reference input.
J3
GND
-
Power Ground reference for logic and I/O pins.
J10
GND
-
Power Ground reference for logic and I/O pins.
July 24, 2012
755
Texas Instruments-Production Data