LM3S6G11 Datasheet, PDF (11/827 Pages) Texas Instruments – Stellaris® LM3S6G11 Microcontroller

OBSOLETE: TI has discontinued production of this device.
Stellaris^® LM3S6G11 Microcontroller
Figure 13-2. TI Synchronous Serial Frame Format (Single Transfer) ........................................ 583
Figure 13-3. TI Synchronous Serial Frame Format (Continuous Transfer) ................................ 583
Figure 13-4. Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 .......................... 584
Figure 13-5. Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 .................. 584
Figure 13-6. Freescale SPI Frame Format with SPO=0 and SPH=1 ......................................... 585
Figure 13-7. Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 ............... 586
Figure 13-8. Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 ........ 586
Figure 13-9. Freescale SPI Frame Format with SPO=1 and SPH=1 ......................................... 587
Figure 13-10. MICROWIRE Frame Format (Single Frame) ........................................................ 588
Figure 13-11. MICROWIRE Frame Format (Continuous Transfer) ............................................. 589
Figure 13-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements ............ 589
Figure 14-1. I²C Block Diagram ............................................................................................. 621
Figure 14-2. I²C Bus Configuration ........................................................................................ 622
Figure 14-3. START and STOP Conditions ............................................................................. 623
Figure 14-4. Complete Data Transfer with a 7-Bit Address ....................................................... 623
Figure 14-5. R/S Bit in First Byte ............................................................................................ 624
Figure 14-6. Data Validity During Bit Transfer on the I²C Bus ................................................... 624
Figure 14-7. Master Single TRANSMIT .................................................................................. 628
Figure 14-8. Master Single RECEIVE ..................................................................................... 629
Figure 14-9. Master TRANSMIT with Repeated START ........................................................... 630
Figure 14-10. Master RECEIVE with Repeated START ............................................................. 631
Figure 14-11. Master RECEIVE with Repeated START after TRANSMIT with Repeated
START .............................................................................................................. 632
Figure 14-12. Master TRANSMIT with Repeated START after RECEIVE with Repeated
START .............................................................................................................. 633
Figure 14-13. Slave Command Sequence ................................................................................ 634
Figure 15-1. Ethernet Controller ............................................................................................. 659
Figure 15-2. Ethernet Controller Block Diagram ...................................................................... 659
Figure 15-3. Ethernet Frame ................................................................................................. 661
Figure 15-4. Interface to an Ethernet Jack .............................................................................. 668
Figure 16-1. Analog Comparator Module Block Diagram ......................................................... 717
Figure 16-2. Structure of Comparator Unit .............................................................................. 719
Figure 16-3. Comparator Internal Reference Structure ............................................................ 719
Figure 17-1. 100-Pin LQFP Package Pin Diagram .................................................................. 729
Figure 17-2. 108-Ball BGA Package Pin Diagram (Top View) ................................................... 730
Figure 20-1. Load Conditions ................................................................................................ 775
Figure 20-2. JTAG Test Clock Input Timing ............................................................................. 776
Figure 20-3. JTAG Test Access Port (TAP) Timing .................................................................. 776
Figure 20-4. Power-On Reset Timing ..................................................................................... 777
Figure 20-5. Brown-Out Reset Timing .................................................................................... 777
Figure 20-6. Power-On Reset and Voltage Parameters ........................................................... 778
Figure 20-7. External Reset Timing (RST) .............................................................................. 778
Figure 20-8. Software Reset Timing ....................................................................................... 778
Figure 20-9. Watchdog Reset Timing ..................................................................................... 779
Figure 20-10. MOSC Failure Reset Timing ............................................................................... 779
Figure 20-11. Hibernation Module Timing with Internal Oscillator Running in Hibernation ............ 783
Figure 20-12. Hibernation Module Timing with Internal Oscillator Stopped in Hibernation ............ 783
July 24, 2012
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Texas Instruments-Production Data