LM3S6G11 Datasheet, PDF (399/827 Pages) Texas Instruments – Stellaris® LM3S6G11 Microcontroller

OBSOLETE: TI has discontinued production of this device.
Stellaris^® LM3S6G11 Microcontroller
9.3 Initialization and Configuration
The GPIO modules may be accessed via two different memory apertures. The legacy aperture, the
Advanced Peripheral Bus (APB), is backwards-compatible with previous Stellaris parts. The other
aperture, the Advanced High-Performance Bus (AHB), offers the same register map but provides
better back-to-back access performance than the APB bus. These apertures are mutually exclusive.
The aperture enabled for a given GPIO port is controlled by the appropriate bit in the GPIOHBCTL
register (see page 203).
To use the pins in a particular GPIO port, the clock for the port must be enabled by setting the
appropriate GPIO Port bit field (GPIOn) in the RCGC2 register (see page 248).
When the internal POR signal is asserted and until otherwise configured, all GPIO pins are configured
to be undriven (tristate): GPIOAFSEL=0, GPIODEN=0, GPIOPDR=0, and GPIOPUR=0, except for
the pins shown in Table 9-1 on page 392. Table 9-4 on page 399 shows all possible configurations
of the GPIO pads and the control register settings required to achieve them. Table 9-5 on page 399
shows how a rising edge interrupt is configured for pin 2 of a GPIO port.
Table 9-4. GPIO Pad Configuration Examples
Configuration
Digital Input (GPIO)
GPIO Register Bit Value^a
AFSEL DIR
ODR
0
0
0
DEN
1
Digital Output (GPIO)
0
1
0
1
Open Drain Output
0
1
1
1
(GPIO)
Open Drain
1
X
1
1
Input/Output (I²C)
Digital Input (Timer
1
X
0
1
CCP)
Digital Output (Timer
1
X
0
1
PWM)
Digital Input/Output
1
X
0
1
(SSI)
Digital Input/Output
1
X
0
1
(UART)
Analog Input
(Comparator)
0
0
0
0
Digital Output
(Comparator)
1
X
0
1
a. X=Ignored (don’t care bit)
?=Can be either 0 or 1, depending on the configuration
PUR
?
?
X
X
?
?
?
?
0
?
PDR
?
?
X
X
?
?
?
?
0
?
DR2R
X
?
?
?
X
?
?
?
X
?
DR4R
X
?
?
?
X
?
?
?
X
?
DR8R
X
?
?
?
X
?
?
?
X
?
SLR
X
?
?
?
X
?
?
?
X
?
Table 9-5. GPIO Interrupt Configuration Example
Register
Desired Interrupt
Event Trigger
Pin 2 Bit Value^a
7
6
GPIOIS
0=edge
1=level
X
X
GPIOIBE
0=single edge
X
X
1=both edges
5
X
X
4
X
X
3
X
X
2
0
0
1
X
X
0
X
X
July 24, 2012
399
Texas Instruments-Production Data