LM3S6G11 Datasheet, PDF (670/827 Pages) Texas Instruments – Stellaris® LM3S6G11 Microcontroller

Ethernet Controller
OBSOLETE: TI has discontinued production of this device.
be enabled before the registers can be programmed (see page 248). There must be a delay of 3
system clocks after the Ethernet module clock is enabled before any Ethernet module registers are
accessed. In addition, the Ethernet oscillator is powered down when the EPHY0 bit in the Run Mode
Clock Gating Control Register 2 (RCGC2) register is clear. After setting the EPHY0 bit, software
must wait 3.5 ms before accessing any of the MII Management registers.
The IEEE 802.3 standard specifies a register set for controlling and gathering status from the PHY
layer. The registers are collectively known as the MII Management registers and are detailed in
Section 22.2.4 of the IEEE 802.3 specification. Table 15-4 on page 670 also lists these MII
Management registers. All addresses given are absolute and are written directly to the REGADR field
of the Ethernet MAC Management Control (MACMCTL) register. The format of registers 0 to 15
are defined by the IEEE specification and are common to all PHY layer implementations. The only
variance allowed is for features that may or may not be supported by a specific PHY implementation.
Registers 16 to 31 are vendor-specific registers, used to support features that are specific to a
vendor's PHY implementation.
Table 15-4. Ethernet Register Map
Offset Name
Type
Reset
Ethernet MAC (Ethernet Offset)
0x000 MACRIS/MACIACK
R/W1C 0x0000.0000
0x004 MACIM
R/W
0x0000.007F
0x008 MACRCTL
R/W
0x0000.0008
0x00C MACTCTL
R/W
0x0000.0000
0x010 MACDATA
R/W
0x0000.0000
0x014 MACIA0
R/W
0x0000.0000
0x018 MACIA1
R/W
0x0000.0000
0x01C MACTHR
R/W
0x0000.003F
0x020 MACMCTL
R/W
0x0000.0000
0x024 MACMDV
R/W
0x0000.0080
0x02C MACMTXD
R/W
0x0000.0000
0x030 MACMRXD
R/W
0x0000.0000
0x034 MACNP
RO
0x0000.0000
0x038 MACTR
R/W
0x0000.0000
0x040 MACLED
R/W
0x0000.0100
0x044 MDIX
R/W
0x0000.0000
MII Management (Accessed through the MACMCTL register)
-
MR0
R/W
0x1000
-
MR1
RO
0x7809
-
MR2
RO
0x0161
Description
See
page
Ethernet MAC Raw Interrupt Status/Acknowledge
672
Ethernet MAC Interrupt Mask
675
Ethernet MAC Receive Control
677
Ethernet MAC Transmit Control
679
Ethernet MAC Data
681
Ethernet MAC Individual Address 0
683
Ethernet MAC Individual Address 1
684
Ethernet MAC Threshold
685
Ethernet MAC Management Control
687
Ethernet MAC Management Divider
689
Ethernet MAC Management Transmit Data
690
Ethernet MAC Management Receive Data
691
Ethernet MAC Number of Packets
692
Ethernet MAC Transmission Request
693
Ethernet MAC LED Encoding
694
Ethernet PHY MDIX
696
Ethernet PHY Management Register 0 – Control
697
Ethernet PHY Management Register 1 – Status
699
Ethernet PHY Management Register 2 – PHY Identifier
1
701
670
July 24, 2012
Texas Instruments-Production Data