LM3S6G11 Datasheet, PDF (398/827 Pages) Texas Instruments – Stellaris® LM3S6G11 Microcontroller

OBSOLETE: TI has discontinued production of this device.
General-Purpose Input/Outputs (GPIOs)
9.2.3
9.2.4
9.2.5
9.2.6
■ GPIO Interrupt Both Edges (GPIOIBE) register (see page 406)
■ GPIO Interrupt Event (GPIOIEV) register (see page 407)
Interrupts are enabled/disabled via the GPIO Interrupt Mask (GPIOIM) register (see page 408).
When an interrupt condition occurs, the state of the interrupt signal can be viewed in two locations:
the GPIO Raw Interrupt Status (GPIORIS) and GPIO Masked Interrupt Status (GPIOMIS) registers
(see page 409 and page 410). As the name implies, the GPIOMIS register only shows interrupt
conditions that are allowed to be passed to the interrupt controller. The GPIORIS register indicates
that a GPIO pin meets the conditions for an interrupt, but has not necessarily been sent to the
interrupt controller.
Interrupts are cleared by writing a 1 to the appropriate bit of the GPIO Interrupt Clear (GPIOICR)
register (see page 411).
When programming the interrupt control registers (GPIOIS, GPIOIBE, or GPIOIEV), the interrupts
should be masked (GPIOIM cleared). Writing any value to an interrupt control register can generate
a spurious interrupt if the corresponding bits are enabled.
Mode Control
The GPIO pins can be controlled by either software or hardware. Software control is the default for
most signals and corresponds to the GPIO mode, where the GPIODATA register is used to read
or write the corresponding pins. When hardware control is enabled via the GPIO Alternate Function
Select (GPIOAFSEL) register (see page 412), the pin state is controlled by its alternate function
(that is, the peripheral).
Further pin muxing options are provided through the GPIO Port Control (GPIOPCTL) register which
selects one of several peripheral functions for each GPIO. For information on the configuration
options, refer to Table 18-5 on page 749.
Commit Control
The GPIO commit control registers provide a layer of protection against accidental programming of
critical hardware peripherals. Protection is provided for the NMI pin (PB7) and the four JTAG/SWD
pins (PC[3:0]). Writes to protected bits of the GPIO Alternate Function Select (GPIOAFSEL)
register (see page 412), GPIO Pull Up Select (GPIOPUR) register (see page 418), GPIO Pull-Down
Select (GPIOPDR) register (see page 420), and GPIO Digital Enable (GPIODEN) register (see
page 423) are not committed to storage unless the GPIO Lock (GPIOLOCK) register (see page 425)
has been unlocked and the appropriate bits of the GPIO Commit (GPIOCR) register (see page 426)
have been set.
Pad Control
The pad control registers allow software to configure the GPIO pads based on the application
requirements. The pad control registers include the GPIODR2R, GPIODR4R, GPIODR8R, GPIOODR,
GPIOPUR, GPIOPDR, GPIOSLR, and GPIODEN registers. These registers control drive strength,
open-drain configuration, pull-up and pull-down resistors, slew-rate control and digital input enable
for each GPIO.
Identification
The identification registers configured at reset allow software to detect and identify the module as
a GPIO block. The identification registers include the GPIOPeriphID0-GPIOPeriphID7 registers as
well as the GPIOPCellID0-GPIOPCellID3 registers.
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July 24, 2012
Texas Instruments-Production Data