LM3S6G11 Datasheet, PDF(736/827 Page) Texas Instruments – Stellaris® LM3S6G11 Microcontroller

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LM3S6G11 Datasheet, PDF (736/827 Pages) Texas Instruments – Stellaris® LM3S6G11 Microcontroller

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Signal Tables

OBSOLETE: TI has discontinued production of this device.

Table 18-2. Signals by Pin Number (continued)

Pin Number

Pin Name

Pin Type Buffer Typea Description

VDDC

62

-

Power Positive supply for most of the logic function, including the

processor core and most peripherals. The voltage on this pin is

1.3 V and is supplied by the on-chip LDO. The VDDC pins should

only be connected to the LDO pin and an external capacitor as

specified in Table 20-6 on page 779 .

63

GND

-

Power Ground reference for logic and I/O pins.

64

RST

I

TTL

System reset input.

65

CMOD0

I

TTL

CPU Mode bit 0. Input must be set to logic 0 (grounded); other

encodings reserved.

PB0

I/O

TTL

GPIO port B bit 0. This pin is not 5-V tolerant.

66

CCP0

I/O

TTL

Capture/Compare/PWM 0.

U1Rx

I

TTL

UART module 1 receive. When in IrDA mode, this signal has IrDA

modulation.

PB1

I/O

TTL

GPIO port B bit 1. This pin is not 5-V tolerant.

CCP1

I/O

TTL

Capture/Compare/PWM 1.

67

CCP2

I/O

TTL

Capture/Compare/PWM 2.

U1Tx

O

TTL

UART module 1 transmit. When in IrDA mode, this signal has IrDA

modulation.

68

VDD

-

Power Positive supply for I/O and some logic.

69

GND

-

Power Ground reference for logic and I/O pins.

PB2

I/O

TTL

GPIO port B bit 2.

CCP0

I/O

TTL

Capture/Compare/PWM 0.

70

CCP3

I/O

TTL

Capture/Compare/PWM 3.

I2C0SCL

I/O

OD

I2C module 0 clock.

PB3

I/O

TTL

GPIO port B bit 3.

71

I2C0SDA

I/O

OD

I2C module 0 data.

PE0

I/O

TTL

GPIO port E bit 0.

72

CCP3

I/O

TTL

Capture/Compare/PWM 3.

SSI1Clk

I/O

TTL

SSI module 1 clock

PE1

I/O

TTL

GPIO port E bit 1.

CCP2

I/O

TTL

Capture/Compare/PWM 2.

73

CCP6

I/O

TTL

Capture/Compare/PWM 6.

SSI1Fss

I/O

TTL

SSI module 1 frame signal

PE2

I/O

TTL

GPIO port E bit 2.

CCP2

I/O

TTL

Capture/Compare/PWM 2.

74

CCP4

I/O

TTL

Capture/Compare/PWM 4.

SSI1Rx

I

TTL

SSI module 1 receive

PE3

I/O

TTL

GPIO port E bit 3.

CCP1

I/O

TTL

Capture/Compare/PWM 1.

75

CCP7

I/O

TTL

Capture/Compare/PWM 7.

SSI1Tx

O

TTL

SSI module 1 transmit

76

CMOD1

I

TTL

CPU Mode bit 1. Input must be set to logic 0 (grounded); other

encodings reserved.

736

July 24, 2012

Texas Instruments-Production Data

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