LM3S6G11 Datasheet, PDF (19/827 Pages) Texas Instruments – Stellaris® LM3S6G11 Microcontroller

OBSOLETE: TI has discontinued production of this device.
Stellaris^® LM3S6G11 Microcontroller
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Device Capabilities 0 (DC0), offset 0x008 ........................................................................ 216
Device Capabilities 1 (DC1), offset 0x010 ........................................................................ 217
Device Capabilities 2 (DC2), offset 0x014 ........................................................................ 219
Device Capabilities 3 (DC3), offset 0x018 ........................................................................ 221
Device Capabilities 4 (DC4), offset 0x01C ....................................................................... 223
Device Capabilities 5 (DC5), offset 0x020 ........................................................................ 225
Device Capabilities 6 (DC6), offset 0x024 ........................................................................ 226
Device Capabilities 7 (DC7), offset 0x028 ........................................................................ 227
Device Capabilities 8 ADC Channels (DC8), offset 0x02C ................................................ 231
Non-Volatile Memory Information (NVMSTAT), offset 0x1A0 ............................................. 232
Run Mode Clock Gating Control Register 0 (RCGC0), offset 0x100 ................................... 233
Sleep Mode Clock Gating Control Register 0 (SCGC0), offset 0x110 ................................. 235
Deep Sleep Mode Clock Gating Control Register 0 (DCGC0), offset 0x120 ....................... 237
Run Mode Clock Gating Control Register 1 (RCGC1), offset 0x104 ................................... 239
Sleep Mode Clock Gating Control Register 1 (SCGC1), offset 0x114 ................................. 242
Deep-Sleep Mode Clock Gating Control Register 1 (DCGC1), offset 0x124 ....................... 245
Run Mode Clock Gating Control Register 2 (RCGC2), offset 0x108 ................................... 248
Sleep Mode Clock Gating Control Register 2 (SCGC2), offset 0x118 ................................. 250
Deep Sleep Mode Clock Gating Control Register 2 (DCGC2), offset 0x128 ....................... 252
Software Reset Control 0 (SRCR0), offset 0x040 ............................................................. 254
Software Reset Control 1 (SRCR1), offset 0x044 ............................................................. 255
Software Reset Control 2 (SRCR2), offset 0x048 ............................................................. 257
Hibernation Module ..................................................................................................................... 259
Register 1: Hibernation RTC Counter (HIBRTCC), offset 0x000 ......................................................... 270
Register 2: Hibernation RTC Match 0 (HIBRTCM0), offset 0x004 ....................................................... 271
Register 3: Hibernation RTC Match 1 (HIBRTCM1), offset 0x008 ....................................................... 272
Register 4: Hibernation RTC Load (HIBRTCLD), offset 0x00C ........................................................... 273
Register 5: Hibernation Control (HIBCTL), offset 0x010 ..................................................................... 274
Register 6: Hibernation Interrupt Mask (HIBIM), offset 0x014 ............................................................. 277
Register 7: Hibernation Raw Interrupt Status (HIBRIS), offset 0x018 .................................................. 279
Register 8: Hibernation Masked Interrupt Status (HIBMIS), offset 0x01C ............................................ 281
Register 9: Hibernation Interrupt Clear (HIBIC), offset 0x020 ............................................................. 283
Register 10: Hibernation RTC Trim (HIBRTCT), offset 0x024 ............................................................... 284
Register 11: Hibernation Data (HIBDATA), offset 0x030-0x12C ............................................................ 285
Internal Memory ........................................................................................................................... 286
Register 1: Flash Memory Address (FMA), offset 0x000 .................................................................... 296
Register 2: Flash Memory Data (FMD), offset 0x004 ......................................................................... 297
Register 3: Flash Memory Control (FMC), offset 0x008 ..................................................................... 298
Register 4: Flash Controller Raw Interrupt Status (FCRIS), offset 0x00C ............................................ 301
Register 5: Flash Controller Interrupt Mask (FCIM), offset 0x010 ........................................................ 302
Register 6: Flash Controller Masked Interrupt Status and Clear (FCMISC), offset 0x014 ..................... 303
Register 7: Flash Memory Control 2 (FMC2), offset 0x020 ................................................................. 304
Register 8: Flash Write Buffer Valid (FWBVAL), offset 0x030 ............................................................. 305
Register 9: Flash Control (FCTL), offset 0x0F8 ................................................................................. 306
Register 10: Flash Write Buffer n (FWBn), offset 0x100 - 0x17C .......................................................... 307
Register 11: ROM Control (RMCTL), offset 0x0F0 .............................................................................. 308
Register 12: Flash Memory Protection Read Enable 0 (FMPRE0), offset 0x130 and 0x200 ................... 309
Register 13: Flash Memory Protection Program Enable 0 (FMPPE0), offset 0x134 and 0x400 ............... 310
July 24, 2012
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