LM3S6G11 Datasheet, PDF (523/827 Pages) Texas Instruments – Stellaris® LM3S6G11 Microcontroller

OBSOLETE: TI has discontinued production of this device.
Stellaris^® LM3S6G11 Microcontroller
Figure 12-4. LIN Message
Message Frame
Synch
Break
Header
Synch Field Ident Field
Data
Field(s)
Response
Data Field
Checksum
Field
In-Frame
Response
Interbyte
Space
The UART should be configured as followed to operate in LIN mode:
1. Configure the UART for 1 start bit, 8 data bits, no parity, and 1 stop bit. Enable the Transmit
FIFO.
2. Set the LIN bit in the UARTCTL register.
When preparing to send a LIN message, the TXFIFO should contain the Sync data (0x55) at FIFO
location 0 and the Identifier data at location 1, followed by the data to be transmitted, and with the
checksum in the final FIFO entry.
12.3.7.1
LIN Master
The UART is enabled to be the LIN master by setting the MASTER bit in the UARTLCTL register.
The length of the Sync Break is programmable using the BLEN field in the UARTLCTL register and
can be 13-16 bits (baud clock cycles).
12.3.7.2
LIN Slave
The LIN UART slave is required to adjust its baud rate to that of the LIN master. In slave mode, the
LIN UART recognizes the Sync Break, which must be at least 13 bits in duration. A timer is provided
to capture timing data on the 1st and 5th falling edges of the Sync field so that the baud rate can
be adjusted to match the master.
After detecting a Sync Break, the UART waits for the synchronization field. The first falling edge
generates an interrupt using the LME1RIS bit in the UARTRIS register, and the timer value is
captured and stored in the UARTLSS register (T1). On the fifth falling edge, a second interrupt is
generated using the LME5RIS bit in the UARTRIS register, and the timer value is captured again
(T2). The actual baud rate can be calculated using (T2-T1)/8, and the local baud rate should be
adjusted as needed. Figure 12-5 on page 524 illustrates the synchronization field.
July 24, 2012
523
Texas Instruments-Production Data