LM3S6G11 Datasheet, PDF (584/827 Pages) Texas Instruments – Stellaris® LM3S6G11 Microcontroller

OBSOLETE: TI has discontinued production of this device.
Synchronous Serial Interface (SSI)
SPO Clock Polarity Bit
When the SPO clock polarity control bit is clear, it produces a steady state Low value on the SSIClk
pin. If the SPO bit is set, a steady state High value is placed on the SSIClk pin when data is not
being transferred.
SPH Phase Control Bit
The SPH phase control bit selects the clock edge that captures data and allows it to change state.
The state of this bit has the most impact on the first bit transmitted by either allowing or not allowing
a clock transition before the first data capture edge. When the SPH phase control bit is clear, data
is captured on the first clock edge transition. If the SPH bit is set, data is captured on the second
clock edge transition.
13.3.4.3
Freescale SPI Frame Format with SPO=0 and SPH=0
Single and continuous transmission signal sequences for Freescale SPI format with SPO=0 and
SPH=0 are shown in Figure 13-4 on page 584 and Figure 13-5 on page 584.
Figure 13-4. Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0
SSIClk
SSIFss
SSIRx
SSITx
MSB
MSB
4 to 16 bits
LSB Q
LSB
Note: Q is undefined.
Figure 13-5. Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0
SSIClk
SSIFss
SSIRx _LSB
SSITx LSB
MSB
MSB
4 to16 bits
LSB
LSB
MSB
MSB
In this configuration, during idle periods:
■ SSIClk is forced Low
■ SSIFss is forced High
■ The transmit data line SSITx is arbitrarily forced Low
■ When the SSI is configured as a master, it enables the SSIClk pad
584
July 24, 2012
Texas Instruments-Production Data