LM3S1N16 Datasheet, PDF (74/794 Pages) Texas Instruments – Stellaris® LM3S1N16 Microcontroller

The Cortex-M3 Processor
Table 2-4. Memory Map (continued)
Start
End
0xE000.F000
0xE004.0000
0xE004.1000
0xE003.FFFF
0xE004.0FFF
0xFFFF.FFFF
Description
Reserved
Trace Port Interface Unit (TPIU)
Reserved
For details,
see page ...
-
56
-
2.4.1
Memory Regions, Types and Attributes
The memory map and the programming of the MPU split the memory map into regions. Each region
has a defined memory type, and some regions have additional memory attributes. The memory
type and attributes determine the behavior of accesses to the region.
The memory types are:
■ Normal: The processor can re-order transactions for efficiency and perform speculative reads.
■ Device: The processor preserves transaction order relative to other transactions to Device or
Strongly Ordered memory.
■ Strongly Ordered: The processor preserves transaction order relative to all other transactions.
The different ordering requirements for Device and Strongly Ordered memory mean that the memory
system can buffer a write to Device memory but must not buffer a write to Strongly Ordered memory.
An additional memory attribute is Execute Never (XN), which means the processor prevents
instruction accesses. A fault exception is generated only on execution of an instruction executed
from an XN region.
2.4.2
Memory System Ordering of Memory Accesses
For most memory accesses caused by explicit memory access instructions, the memory system
does not guarantee that the order in which the accesses complete matches the program order of
the instructions, providing the order does not affect the behavior of the instruction sequence. Normally,
if correct program execution depends on two memory accesses completing in program order,
software must insert a memory barrier instruction between the memory access instructions (see
“Software Ordering of Memory Accesses” on page 75).
However, the memory system does guarantee ordering of accesses to Device and Strongly Ordered
memory. For two memory access instructions A1 and A2, if both A1 and A2 are accesses to either
Device or Strongly Ordered memory, and if A1 occurs before A2 in program order, A1 is always
observed before A2.
2.4.3
Behavior of Memory Accesses
Table 2-5 on page 75 shows the behavior of accesses to each region in the memory map. See
“Memory Regions, Types and Attributes” on page 74 for more information on memory types and
the XN attribute. Stellaris devices may have reserved memory areas within the address ranges
shown below (refer to Table 2-4 on page 72 for more information).
74
January 21, 2012
Texas Instruments-Production Data