LM3S1N16 Datasheet, PDF (294/794 Pages) Texas Instruments – Stellaris® LM3S1N16 Microcontroller

Internal Memory
7.2.3.2
■ Flash Memory Protection Program Enable (FMPPEn): If a bit is set, the corresponding block
may be programmed (written) or erased. If a bit is cleared, the corresponding block may not be
changed.
■ Flash Memory Protection Read Enable (FMPREn): If a bit is set, the corresponding block may
be executed or read by software or debuggers. If a bit is cleared, the corresponding block may
only be executed, and contents of the memory block are prohibited from being read as data.
The policies may be combined as shown in Table 7-1 on page 294.
Table 7-1. Flash Memory Protection Policy Combinations
FMPPEn
0
1
0
1
FMPREn
0
0
1
1
Protection
Execute-only protection. The block may only be executed and may not be written or erased.
This mode is used to protect code.
The block may be written, erased or executed, but not read. This combination is unlikely to
be used.
Read-only protection. The block may be read or executed but may not be written or erased.
This mode is used to lock the block from further modification while allowing any read or
execute access.
No protection. The block may be written, erased, executed or read.
A Flash memory access that attempts to read a read-protected block (FMPREn bit is set) is prohibited
and generates a bus fault. A Flash memory access that attempts to program or erase a
program-protected block (FMPPEn bit is set) is prohibited and can optionally generate an interrupt
(by setting the AMASK bit in the Flash Controller Interrupt Mask (FCIM) register) to alert software
developers of poorly behaving software during the development and debug phases. Note that if a
FMPREn bit is cleared, all read accesses to the Flash memory block are disallowed, including any
data accesses. Care must be taken not to store required data in a Flash memory block that has the
associated FMPREn bit cleared.
The factory settings for the FMPREn and FMPPEn registers are a value of 1 for all implemented
banks. These settings create a policy of open access and programmability. The register bits may
be changed by clearing the specific register bit. The changes are effective immediately, but are not
permanent until the register is committed (saved), at which point the bit change is permanent. If a
bit is changed from a 1 to a 0 and not committed, it may be restored by executing any type of reset
sequence. The changes are committed using the Flash Memory Control (FMC) register. Details
on programming these bits are discussed in “Non-Volatile Register Programming” on page 296.
Interrupts
The Flash memory controller can generate interrupts when the following conditions are observed:
■ Programming Interrupt - signals when a program or erase action is complete.
■ Access Interrupt - signals when a program or erase action has been attempted on a 2-kB block
of memory that is protected by its corresponding FMPPEn bit.
The interrupt events that can trigger a controller-level interrupt are defined in the Flash Controller
Masked Interrupt Status (FCMIS) register (see page 306) by setting the corresponding MASK bits.
If interrupts are not used, the raw interrupt status is always visible via the Flash Controller Raw
Interrupt Status (FCRIS) register (see page 305).
294
January 21, 2012
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