LM3S1N16 Datasheet, PDF (439/794 Pages) Texas Instruments – Stellaris® LM3S1N16 Microcontroller

Stellaris^® LM3S1N16 Microcontroller
Table 10-3. General-Purpose Timer Capabilities
Mode
Timer Use
Count Direction
One-shot
Individual
Concatenated
Up or Down
Up or Down
Periodic
Individual
Concatenated
Up or Down
Up or Down
RTC
Concatenated
Up
Edge Count
Individual
Down
Edge Time
Individual
Down
PWM
Individual
Down
a. The prescaler is only available when the timers are used individually
Counter Size
16-bit
32-bit
16-bit
32-bit
32-bit
16-bit
16-bit
16-bit
Prescaler Size^a
8-bit
-
8-bit
-
-
8-bit
-
-
Software configures the GPTM using the GPTM Configuration (GPTMCFG) register (see page 451),
the GPTM Timer A Mode (GPTMTAMR) register (see page 452), and the GPTM Timer B Mode
(GPTMTBMR) register (see page 454). When in one of the concatentated modes, Timer A and Timer
B can only operate in one mode. However, when configured in an individual mode, Timer A and
Timer B can be independently configured in any combination of the individual modes.
10.3.1
GPTM Reset Conditions
After reset has been applied to the GPTM module, the module is in an inactive state, and all control
registers are cleared and in their default states. Counters Timer A and Timer B are initialized to all
1s, along with their corresponding load registers: the GPTM Timer A Interval Load (GPTMTAILR)
register (see page 469) and the GPTM Timer B Interval Load (GPTMTBILR) register (see page 470)
and shadow registers: the GPTM Timer A Value (GPTMTAV) register (see page 479) and the GPTM
Timer B Value (GPTMTBV) register (see page 480). The prescale counters are initialized to 0x00:
the GPTM Timer A Prescale (GPTMTAPR) register (see page 473) and the GPTM Timer B Prescale
(GPTMTBPR) register (see page 474).
10.3.2
Timer Modes
This section describes the operation of the various timer modes. When using Timer A and Timer B
in concatenated mode, only the Timer A control and status bits must be used; there is no need to
use Timer B control and status bits. The GPTM is placed into individual/split mode by writing a value
of 0x4 to the GPTM Configuration (GPTMCFG) register (see page 451). In the following sections,
the variable "n" is used in bit field and register names to imply either a Timer A function or a Timer
B function. Throughout this section, the timeout event in down-count mode is 0x0 and in up-count
mode is the value in the GPTM Timer n Interval Load (GPTMTnILR) and the optional GPTM Timer
n Prescale (GPTMTnPR) registers.
10.3.2.1
One-Shot/Periodic Timer Mode
The selection of one-shot or periodic mode is determined by the value written to the TnMR field of
the GPTM Timer n Mode (GPTMTnMR) register (see page 452). The timer is configured to count
up or down using the TnCDIR bit in the GPTMTnMR register.
When software sets the TnEN bit in the GPTM Control (GPTMCTL) register (see page 456), the
timer begins counting up from 0x0 or down from its preloaded value. Alternatively, if the TnWOT bit
is set in the GPTMTnMR register, once the TnEN bit is set, the timer waits for a trigger to begin
counting (see the section called “Wait-for-Trigger Mode” on page 441). Table 10-4 on page 440 shows
the values that are loaded into the timer registers when the timer is enabled.
January 21, 2012
439
Texas Instruments-Production Data