LM3S1N16 Datasheet, PDF (172/794 Pages) Texas Instruments – Stellaris® LM3S1N16 Microcontroller

JTAG Interface
4.5.2.4
4.5.2.5
4.5.2.6
Figure 4-5. Boundary Scan Register Format
TDI I
N
O
U
T
O _... I
E
N
O
U
T
O
E
I
N
O
U
T
O _...
E
I
N
O
U
T
O TDO
E
1^st GPIO
m^th GPIO
(m+1)^th GPIO
GPIO n^th
APACC Data Register
The format for the 35-bit APACC Data Register defined by ARM is described in the ARM® Debug
Interface V5 Architecture Specification.
DPACC Data Register
The format for the 35-bit DPACC Data Register defined by ARM is described in the ARM® Debug
Interface V5 Architecture Specification.
ABORT Data Register
The format for the 35-bit ABORT Data Register defined by ARM is described in the ARM® Debug
Interface V5 Architecture Specification.
172
January 21, 2012
Texas Instruments-Production Data