LM3S1N16 Datasheet, PDF (13/794 Pages) Texas Instruments – Stellaris® LM3S1N16 Microcontroller

Stellaris^® LM3S1N16 Microcontroller
List of Tables
Table 1.
Table 2.
Table 2-1.
Table 2-2.
Table 2-3.
Table 2-4.
Table 2-5.
Table 2-6.
Table 2-7.
Table 2-8.
Table 2-9.
Table 2-10.
Table 2-11.
Table 2-12.
Table 2-13.
Table 3-1.
Table 3-2.
Table 3-3.
Table 3-4.
Table 3-5.
Table 3-6.
Table 3-7.
Table 3-8.
Table 3-9.
Table 4-1.
Table 4-2.
Table 4-3.
Table 5-1.
Table 5-2.
Table 5-3.
Table 5-4.
Table 5-5.
Table 5-6.
Table 5-7.
Table 5-8.
Table 6-1.
Table 6-2.
Table 6-3.
Table 7-1.
Table 7-2.
Table 7-3.
Table 8-1.
Table 8-2.
Table 8-3.
Table 8-4.
Table 8-5.
Revision History .................................................................................................. 25
Documentation Conventions ................................................................................ 34
Summary of Processor Mode, Privilege Level, and Stack Use ................................ 58
Processor Register Map ....................................................................................... 59
PSR Register Combinations ................................................................................. 64
Memory Map ....................................................................................................... 72
Memory Access Behavior ..................................................................................... 75
SRAM Memory Bit-Banding Regions .................................................................... 77
Peripheral Memory Bit-Banding Regions ............................................................... 77
Exception Types .................................................................................................. 82
Interrupts ............................................................................................................ 83
Exception Return Behavior ................................................................................... 88
Faults ................................................................................................................. 88
Fault Status and Fault Address Registers .............................................................. 90
Cortex-M3 Instruction Summary ........................................................................... 92
Core Peripheral Register Regions ......................................................................... 95
Memory Attributes Summary ................................................................................ 98
TEX, S, C, and B Bit Field Encoding ................................................................... 101
Cache Policy for Memory Attribute Encoding ....................................................... 102
AP Bit Field Encoding ........................................................................................ 102
Memory Region Attributes for Stellaris Microcontrollers ........................................ 102
Peripherals Register Map ................................................................................... 103
Interrupt Priority Levels ...................................................................................... 130
Example SIZE Field Values ................................................................................ 158
JTAG_SWD_SWO Signals (64LQFP) ................................................................. 162
JTAG Port Pins State after Power-On Reset or RST assertion .............................. 163
JTAG Instruction Register Commands ................................................................. 169
System Control & Clocks Signals (64LQFP) ........................................................ 173
Reset Sources ................................................................................................... 174
Clock Source Options ........................................................................................ 181
Possible System Clock Frequencies Using the SYSDIV Field ............................... 184
Examples of Possible System Clock Frequencies Using the SYSDIV2 Field .......... 184
Examples of Possible System Clock Frequencies with DIV400=1 ......................... 185
System Control Register Map ............................................................................. 189
RCC2 Fields that Override RCC Fields ............................................................... 210
Hibernate Signals (64LQFP) ............................................................................... 265
Hibernation Module Clock Operation ................................................................... 271
Hibernation Module Register Map ....................................................................... 273
Flash Memory Protection Policy Combinations .................................................... 294
User-Programmable Flash Memory Resident Registers ....................................... 298
Flash Register Map ............................................................................................ 298
μDMA Channel Assignments .............................................................................. 329
Request Type Support ....................................................................................... 331
Control Structure Memory Map ........................................................................... 332
Channel Control Structure .................................................................................. 332
μDMA Read Example: 8-Bit Peripheral ................................................................ 341
January 21, 2012
13
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