LM3S1N16 Datasheet, PDF (7/794 Pages) Texas Instruments – Stellaris® LM3S1N16 Microcontroller

Stellaris^® LM3S1N16 Microcontroller
12.3.3 Hardware Sample Averaging Circuit ............................................................................. 510
12.3.4 Analog-to-Digital Converter .......................................................................................... 511
12.3.5 Differential Sampling ................................................................................................... 514
12.3.6 Internal Temperature Sensor ........................................................................................ 517
12.3.7 Digital Comparator Unit ............................................................................................... 517
12.4 Initialization and Configuration ..................................................................................... 521
12.4.1 Module Initialization ..................................................................................................... 521
12.4.2 Sample Sequencer Configuration ................................................................................. 522
12.5 Register Map .............................................................................................................. 522
12.6 Register Descriptions .................................................................................................. 524
13 Universal Asynchronous Receivers/Transmitters (UARTs) ............................. 579
13.1 Block Diagram ............................................................................................................ 580
13.2 Signal Description ....................................................................................................... 580
13.3 Functional Description ................................................................................................. 581
13.3.1 Transmit/Receive Logic ............................................................................................... 581
13.3.2 Baud-Rate Generation ................................................................................................. 582
13.3.3 Data Transmission ...................................................................................................... 582
13.3.4 Serial IR (SIR) ............................................................................................................. 583
13.3.5 ISO 7816 Support ....................................................................................................... 584
13.3.6 LIN Support ................................................................................................................ 584
13.3.7 FIFO Operation ........................................................................................................... 586
13.3.8 Interrupts .................................................................................................................... 586
13.3.9 Loopback Operation .................................................................................................... 587
13.3.10 DMA Operation ........................................................................................................... 587
13.4 Initialization and Configuration ..................................................................................... 588
13.5 Register Map .............................................................................................................. 589
13.6 Register Descriptions .................................................................................................. 590
14 Synchronous Serial Interface (SSI) .................................................................... 635
14.1 Block Diagram ............................................................................................................ 636
14.2 Signal Description ....................................................................................................... 636
14.3 Functional Description ................................................................................................. 637
14.3.1 Bit Rate Generation ..................................................................................................... 637
14.3.2 FIFO Operation ........................................................................................................... 637
14.3.3 Interrupts .................................................................................................................... 638
14.3.4 Frame Formats ........................................................................................................... 639
14.3.5 DMA Operation ........................................................................................................... 646
14.4 Initialization and Configuration ..................................................................................... 647
14.5 Register Map .............................................................................................................. 648
14.6 Register Descriptions .................................................................................................. 649
15 Inter-Integrated Circuit (I²C) Interface ................................................................ 677
15.1 Block Diagram ............................................................................................................ 678
15.2 Signal Description ....................................................................................................... 678
15.3 Functional Description ................................................................................................. 678
15.3.1 I²C Bus Functional Overview ........................................................................................ 679
15.3.2 Available Speed Modes ............................................................................................... 681
15.3.3 Interrupts .................................................................................................................... 682
15.3.4 Loopback Operation .................................................................................................... 683
15.3.5 Command Sequence Flow Charts ................................................................................ 683
January 21, 2012
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