LM3S1N16 Datasheet, PDF (368/794 Pages) Texas Instruments – Stellaris® LM3S1N16 Microcontroller

Micro Direct Memory Access (μDMA)
Register 14: DMA Channel Enable Set (DMAENASET), offset 0x028
Each bit of the DMAENASET register represents the corresponding µDMA channel. Setting a bit
enables the corresponding µDMA channel. Reading the register returns the enable status of the
channels. If a channel is enabled but the request mask is set (DMAREQMASKSET), then the
channel can be used for software-initiated transfers.
DMA Channel Enable Set (DMAENASET)
Base 0x400F.F000
Offset 0x028
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
SET[n]
Type R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SET[n]
Type R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:0
Name
SET[n]
Type
Reset Description
R/W 0x0000.0000 Channel [n] Enable Set
Value Description
0 µDMA Channel [n] is disabled.
1 µDMA Channel [n] is enabled.
Bit 0 corresponds to channel 0. A bit can only be cleared by setting the
corresponding CLR[n] bit in the DMAENACLR register.
368
January 21, 2012
Texas Instruments-Production Data