LM3S1N16 Datasheet, PDF (728/794 Pages) Texas Instruments – Stellaris® LM3S1N16 Microcontroller

Signal Tables
Table 18-2. Signals by Pin Number
Pin Number
1
2
Pin Name
PE3
AIN0
CCP1
SSI1Tx
PE2
AIN1
CCP2
CCP4
SSI1Rx
VDDA
Pin Type
I/O
I
I/O
O
I/O
I
I/O
I/O
I
-
3
GNDA
-
4
PE1
I/O
AIN2
I
5
CCP2
I/O
SSI1Fss
I/O
PE0
I/O
AIN3
I
6
CCP3
I/O
SSI1Clk
I/O
LDO
-
7
PE4
I/O
CCP2
I/O
8
CCP3
I/O
U2Tx
O
VDDC
-
9
10
GND
-
Buffer Type^a Description
TTL
GPIO port E bit 3.
Analog Analog-to-digital converter input 0.
TTL
Capture/Compare/PWM 1.
TTL
SSI module 1 transmit.
TTL
GPIO port E bit 2.
Analog Analog-to-digital converter input 1.
TTL
Capture/Compare/PWM 2.
TTL
Capture/Compare/PWM 4.
TTL
SSI module 1 receive.
Power
The positive supply for the analog circuits (ADC, Analog
Comparators, etc.). These are separated from VDD to minimize
the electrical noise contained on VDD from affecting the analog
functions. VDDA pins must be supplied with a voltage that meets
the specification in Table 20-2 on page 745, regardless of system
implementation.
Power
The ground reference for the analog circuits (ADC, Analog
Comparators, etc.). These are separated from GND to minimize
the electrical noise contained on VDD from affecting the analog
functions.
TTL
GPIO port E bit 1.
Analog Analog-to-digital converter input 2.
TTL
Capture/Compare/PWM 2.
TTL
SSI module 1 frame.
TTL
GPIO port E bit 0.
Analog Analog-to-digital converter input 3.
TTL
Capture/Compare/PWM 3.
TTL
SSI module 1 clock.
Power
Low drop-out regulator output voltage. This pin requires an external
capacitor between the pin and GND of 1 µF or greater. The LDO
pin must also be connected to the VDDC pins at the board level in
addition to the decoupling capacitor(s).
TTL
GPIO port E bit 4.
TTL
Capture/Compare/PWM 2.
TTL
Capture/Compare/PWM 3.
TTL
UART module 2 transmit. When in IrDA mode, this signal has IrDA
modulation.
Power
Positive supply for most of the logic function, including the
processor core and most peripherals. The voltage on this pin is
1.3 V and is supplied by the on-chip LDO. The VDDC pins should
only be connected to the LDO pin and an external capacitor as
specified in Table 20-6 on page 750.
Power Ground reference for logic and I/O pins.
728
January 21, 2012
Texas Instruments-Production Data