LM3S1N16 Datasheet, PDF (11/794 Pages) Texas Instruments – Stellaris® LM3S1N16 Microcontroller

Stellaris^® LM3S1N16 Microcontroller
Figure 12-7. Differential Sampling Range, V_{IN_ODD} = 1.5 V ...................................................... 515
Figure 12-8. Differential Sampling Range, V_{IN_ODD} = 0.75 V .................................................... 516
Figure 12-9. Differential Sampling Range, V_{IN_ODD} = 2.25 V .................................................... 516
Figure 12-10. Internal Temperature Sensor Characteristic ......................................................... 517
Figure 12-11. Low-Band Operation (CIC=0x0) .......................................................................... 519
Figure 12-12. Mid-Band Operation (CIC=0x1) .......................................................................... 520
Figure 12-13. High-Band Operation (CIC=0x3) ......................................................................... 521
Figure 13-1. UART Module Block Diagram ............................................................................. 580
Figure 13-2. UART Character Frame ..................................................................................... 581
Figure 13-3. IrDA Data Modulation ......................................................................................... 584
Figure 13-4. LIN Message ..................................................................................................... 585
Figure 13-5. LIN Synchronization Field ................................................................................... 586
Figure 14-1. SSI Module Block Diagram ................................................................................. 636
Figure 14-2. TI Synchronous Serial Frame Format (Single Transfer) ........................................ 639
Figure 14-3. TI Synchronous Serial Frame Format (Continuous Transfer) ................................ 640
Figure 14-4. Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 .......................... 641
Figure 14-5. Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 .................. 641
Figure 14-6. Freescale SPI Frame Format with SPO=0 and SPH=1 ......................................... 642
Figure 14-7. Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 ............... 643
Figure 14-8. Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 ........ 643
Figure 14-9. Freescale SPI Frame Format with SPO=1 and SPH=1 ......................................... 644
Figure 14-10. MICROWIRE Frame Format (Single Frame) ........................................................ 645
Figure 14-11. MICROWIRE Frame Format (Continuous Transfer) ............................................. 646
Figure 14-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements ............ 646
Figure 15-1. I²C Block Diagram ............................................................................................. 678
Figure 15-2. I²C Bus Configuration ........................................................................................ 679
Figure 15-3. START and STOP Conditions ............................................................................. 679
Figure 15-4. Complete Data Transfer with a 7-Bit Address ....................................................... 680
Figure 15-5. R/S Bit in First Byte ............................................................................................ 680
Figure 15-6. Data Validity During Bit Transfer on the I²C Bus ................................................... 680
Figure 15-7. Master Single TRANSMIT .................................................................................. 684
Figure 15-8. Master Single RECEIVE ..................................................................................... 685
Figure 15-9. Master TRANSMIT with Repeated START ........................................................... 686
Figure 15-10. Master RECEIVE with Repeated START ............................................................. 687
Figure 15-11. Master RECEIVE with Repeated START after TRANSMIT with Repeated
START .............................................................................................................. 688
Figure 15-12. Master TRANSMIT with Repeated START after RECEIVE with Repeated
START .............................................................................................................. 689
Figure 15-13. Slave Command Sequence ................................................................................ 690
Figure 16-1. Analog Comparator Module Block Diagram ......................................................... 714
Figure 16-2. Structure of Comparator Unit .............................................................................. 716
Figure 16-3. Comparator Internal Reference Structure ............................................................ 716
Figure 17-1. 64-Pin LQFP Package Pin Diagram .................................................................... 726
Figure 20-1. Load Conditions ................................................................................................ 746
Figure 20-2. JTAG Test Clock Input Timing ............................................................................. 747
Figure 20-3. JTAG Test Access Port (TAP) Timing .................................................................. 747
Figure 20-4. Power-On Reset Timing ..................................................................................... 748
Figure 20-5. Brown-Out Reset Timing .................................................................................... 748
January 21, 2012
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Texas Instruments-Production Data