LM3S1N16 Datasheet, PDF (312/794 Pages) Texas Instruments – Stellaris® LM3S1N16 Microcontroller

Internal Memory
Register 11: ROM Control (RMCTL), offset 0x0F0
This register provides control of the ROM controller state. This register offset is relative to the System
Control base address of 0x400F.E000.
At reset, the ROM is mapped over the Flash memory so that the ROM boot sequence is always
executed. The boot sequence executed from ROM is as follows:
1. The BA bit (below) is cleared such that ROM is mapped to 0x01xx.xxxx and Flash memory is
mapped to address 0x0.
2. The BOOTCFG register is read. If the EN bit is clear, the status of the specified GPIO pin is
compared with the specified polarity. If the status matches the specified polarity, the ROM is
mapped to address 0x0000.0000 and execution continues out of the ROM Boot Loader.
3. If the status doesn't match the specified polarity, the data at address 0x0000.0004 is read, and
if the data at this address is 0xFFFF.FFFF, the ROM is mapped to address 0x0000.0000 and
execution continues out of the ROM Boot Loader.
4. If there is data at address 0x0000.0004 that is not 0xFFFF.FFFF, the stack pointer (SP) is loaded
from Flash memory at address 0x0000.0000 and the program counter (PC) is loaded from
address 0x0000.0004. The user application begins executing.
ROM Control (RMCTL)
Base 0x400F.E000
Offset 0x0F0
Type R/W1C, reset -
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
BA
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO R/W1C
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
Bit/Field
31:1
0
Name
reserved
BA
Type
Reset Description
RO 0x0000.000 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
R/W1C
1
Boot Alias
Value Description
1 The microcontroller's ROM appears at address 0x0.
0 The Flash memory is at address 0x0.
This bit is cleared by writing a 1 to this bit position.
312
January 21, 2012
Texas Instruments-Production Data