LM3S1N16 Datasheet, PDF (204/794 Pages) Texas Instruments – Stellaris® LM3S1N16 Microcontroller

System Control
Bit/Field
22
21:14
13
12
11
Name
USESYSDIV
reserved
PWRDN
reserved
BYPASS
Type
R/W
RO
R/W
RO
R/W
Reset
0
Description
Enable System Clock Divider
Value Description
1 The system clock divider is the source for the system clock. The
system clock divider is forced to be used when the PLL is
selected as the source.
If the USERCC2 bit in the RCC2 register is set, then the SYSDIV2
field in the RCC2 register is used as the system clock divider
rather than the SYSDIV field in this register.
0 The system clock is used undivided.
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
1
PLL Power Down
Value Description
1 The PLL is powered down. Care must be taken to ensure that
another clock source is functioning and that the BYPASS bit is
set before setting this bit.
0 The PLL is operating normally.
1
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
1
PLL Bypass
Value Description
1 The system clock is derived from the OSC source and divided
by the divisor specified by SYSDIV.
0 The system clock is the PLL output clock divided by the divisor
specified by SYSDIV.
See Table 5-4 on page 184 for programming guidelines.
Note: The ADC must be clocked from the PLL or directly from a
16-MHz clock source to operate properly.
204
January 21, 2012
Texas Instruments-Production Data