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LM3S1N16 Datasheet, PDF (30/794 Pages) Texas Instruments – Stellaris® LM3S1N16 Microcontroller
Revision History
Table 1. Revision History (continued)
Date
May 2010
Revision
7164
Description
■ Added data sheets for five new Stellaris® Tempest-class parts: LM3S1R26, LM3S1621, LM3S1B21,
LM3S9781, and LM3S9B81.
■ Additional minor data sheet clarifications and corrections.
May 2010
7101
■ Added pin table "Possible Pin Assignments for Alternate Functions", which lists the signals based
on number of possible pin assignments. This table can be used to plan how to configure the pins
for a particular functionality.
■ Additional minor data sheet clarifications and corrections.
March 2010
6983
■ Extended TBRL bit field in GPTMTBR register.
■ Removed extraneous 100-pin tables from the chapters.
■ Additional minor data sheet clarifications and corrections.
March 2010
6912
■ Corrected the pin tables in the Signal Description sections within chapters (tables were correct in
Signal Tables chapter but incorrect within chapters).
■ Renamed the USER_DBG register to the BOOTCFG register in the Internal Memory chapter. Added
information on how to use a GPIO pin to force the ROM Boot Loader to execute on reset.
■ Added three figures to the ADC chapter on sample phase control.
■ Corrected the pin name for the VDDC signals, which were mistakenly labelled as VDD25.
February 2010
6790
■ Added 108-ball BGA package.
■ In "System Control" chapter:
– Clarified functional description for external reset and brown-out reset.
– Clarified Debug Access Port operation after Sleep modes.
– Corrected the reset value of the Run-Mode Clock Configuration 2 (RCC2) register.
■ In "Internal Memory" chapter, clarified wording on Flash memory access errors and added a section
on interrupts to the Flash memory description.
■ Added clarification about timer operating modes and added register descriptions for the GPTM
Timer n Prescale Match (GPTMTnPMR) registers.
■ Clarified register descriptions for GPTM Timer A Value (GPTMTAV) and GPTM Timer B Value
(GPTMTBV) registers.
■ Corrected the reset value of the ADC Sample Sequence Result FIFO n (ADCSSFIFOn) registers.
■ Added ADC Sample Phase Control (ADCSPC) register at offset 0x24.
■ Added caution note to the I2C Master Timer Period (I2CMTPR) register description and changed
field width to 7 bits.
■ Made these changes to the Operating Characteristics chapter:
– Added storage temperature ratings to "Temperature Characteristics" table
– Added "ESD Absolute Maximum Ratings" table
■ Made these changes to the Electrical Characteristics chapter:
– In "Flash Memory Characteristics" table, corrected Mass erase time
– Added sleep and deep-sleep wake-up times ("Sleep Modes AC Characteristics" table)
– In "Reset Characteristics" table, corrected units for supply voltage (VDD) rise time
– Added table entry for VDD3ON power consumption to Table 20-28 on page 760.
■ Added additional DriverLib functions to appendix.
30
January 21, 2012
Texas Instruments-Production Data