LM3S1N16 Datasheet, PDF (293/794 Pages) Texas Instruments – Stellaris® LM3S1N16 Microcontroller

Stellaris^® LM3S1N16 Microcontroller
7.2.2.3
7.2.2.4
7.2.3
7.2.3.1
Advanced Encryption Standard (AES) Cryptography Tables
AES is a strong encryption method with reasonable performance and size. AES is fast in both
hardware and software, is fairly easy to implement, and requires little memory. AES is ideal for
applications that can use pre-arranged keys, such as setup during manufacturing or configuration.
Four data tables used by the XySSL AES implementation are provided in the ROM. The first is the
forward S-box substitution table, the second is the reverse S-box substitution table, the third is the
forward polynomial table, and the final is the reverse polynomial table. See the Stellaris® ROM
User’s Guide for more information on AES.
Cyclic Redundancy Check (CRC) Error Detection
The CRC technique can be used to validate correct receipt of messages (nothing lost or modified
in transit), to validate data after decompression, to validate that Flash memory contents have not
been changed, and for other cases where the data needs to be validated. A CRC is preferred over
a simple checksum (e.g. XOR all bits) because it catches changes more readily. See the Stellaris®
ROM User’s Guide for more information on CRC.
Flash Memory
The Flash memory is organized as a set of 1-KB blocks that can be individually erased. An individual
32-bit word can be programmed to change bits from 1 to 0. In addition, a write buffer provides the
ability to concurrently program 32 continuous words in Flash memory. Erasing a block causes the
entire contents of the block to be reset to all 1s. The 1-KB blocks are paired into sets of 2-KB blocks
that can be individually protected. The protection allows blocks to be marked as read-only or
execute-only, providing different levels of code protection. Read-only blocks cannot be erased or
programmed, protecting the contents of those blocks from being modified. Execute-only blocks
cannot be erased or programmed and can only be read by the controller instruction fetch mechanism,
protecting the contents of those blocks from being read by either the controller or by a debugger.
Caution – The Stellaris Flash memory array has ECC which uses a test port into the Flash memory to
continually scan the array for ECC errors and to correct any that are detected. This operation is
transparent to the microcontroller. The BIST must scan the entire memory array occasionally to ensure
integrity, taking about five minutes to do so. In systems where the microcontroller is frequently powered
for less than five minutes, power should be removed from the microcontroller in a controlled manner
to ensure proper operation. This controlled manner can either be through entering Hibernate mode or
software can request permission to power down the part using the USDREQ bit in the Flash Control
(FCTL) register and wait to receive an acknowledge from the USDACK bit prior to removing power. If
the microcontroller is powered down using this controlled method, the BIST engine keeps track of
where it was in the memory array and it always scans the complete array after any aggregate of five
minutes powered-on, regardless of the number of intervening power cycles. If the microcontroller is
powered down before five minutes of being powered up, BIST starts again from wherever it left off
before the last controlled power-down or from 0 if there never was a controlled power down. An
occasional short power down is not a concern, but the microcontroller should not always be powered
down frequently in an uncontrolled manner. The microcontroller can be power-cycled as frequently
as necessary if it is powered-down in a controlled manner.
Flash Memory Protection
The user is provided two forms of Flash memory protection per 2-KB Flash memory block in one
pair of 32-bit wide registers. The policy for each protection form is controlled by individual bits (per
policy per block) in the FMPPEn and FMPREn registers.
January 21, 2012
293
Texas Instruments-Production Data