LM3S1N16 Datasheet, PDF (5/794 Pages) Texas Instruments – Stellaris® LM3S1N16 Microcontroller

Stellaris^® LM3S1N16 Microcontroller
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Hibernation Module .............................................................................................. 264
6.1 Block Diagram ............................................................................................................ 265
6.2 Signal Description ....................................................................................................... 265
6.3 Functional Description ................................................................................................. 266
6.3.1 Register Access Timing ............................................................................................... 266
6.3.2 Hibernation Clock Source ............................................................................................ 266
6.3.3 System Implementation ............................................................................................... 268
6.3.4 Battery Management ................................................................................................... 268
6.3.5 Real-Time Clock .......................................................................................................... 269
6.3.6 Battery-Backed Memory .............................................................................................. 269
6.3.7 Power Control Using HIB ............................................................................................. 269
6.3.8 Power Control Using VDD3ON Mode ........................................................................... 270
6.3.9 Initiating Hibernate ...................................................................................................... 270
6.3.10 Waking from Hibernate ................................................................................................ 270
6.3.11 Interrupts and Status ................................................................................................... 270
6.4 Initialization and Configuration ..................................................................................... 271
6.4.1 Initialization ................................................................................................................. 271
6.4.2 RTC Match Functionality (No Hibernation) .................................................................... 272
6.4.3 RTC Match/Wake-Up from Hibernation ......................................................................... 272
6.4.4 External Wake-Up from Hibernation .............................................................................. 272
6.4.5 RTC or External Wake-Up from Hibernation .................................................................. 272
6.5 Register Map .............................................................................................................. 273
6.6 Register Descriptions .................................................................................................. 273
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7.1
7.2
7.2.1
7.2.2
7.2.3
7.3
7.4
7.5
Internal Memory ................................................................................................... 290
Block Diagram ............................................................................................................ 290
Functional Description ................................................................................................. 290
SRAM ........................................................................................................................ 291
ROM .......................................................................................................................... 291
Flash Memory ............................................................................................................. 293
Register Map .............................................................................................................. 298
Flash Memory Register Descriptions (Flash Control Offset) ............................................ 299
Memory Register Descriptions (System Control Offset) .................................................. 311
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Micro Direct Memory Access (μDMA) ................................................................ 327
8.1 Block Diagram ............................................................................................................ 328
8.2 Functional Description ................................................................................................. 328
8.2.1 Channel Assignments .................................................................................................. 329
8.2.2 Priority ........................................................................................................................ 330
8.2.3 Arbitration Size ............................................................................................................ 330
8.2.4 Request Types ............................................................................................................ 330
8.2.5 Channel Configuration ................................................................................................. 331
8.2.6 Transfer Modes ........................................................................................................... 333
8.2.7 Transfer Size and Increment ........................................................................................ 341
8.2.8 Peripheral Interface ..................................................................................................... 341
8.2.9 Software Request ........................................................................................................ 341
8.2.10 Interrupts and Errors .................................................................................................... 342
8.3 Initialization and Configuration ..................................................................................... 342
8.3.1 Module Initialization ..................................................................................................... 342
8.3.2 Configuring a Memory-to-Memory Transfer ................................................................... 342
January 21, 2012
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