LM3S1N16 Datasheet, PDF (3/794 Pages) Texas Instruments – Stellaris® LM3S1N16 Microcontroller

Stellaris^® LM3S1N16 Microcontroller
Table of Contents
Revision History ............................................................................................................................. 25
About This Document .................................................................................................................... 33
Audience .............................................................................................................................................. 33
About This Manual ................................................................................................................................ 33
Related Documents ............................................................................................................................... 33
Documentation Conventions .................................................................................................................. 34
1
1.1
1.2
1.3
1.3.1
1.3.2
1.3.3
1.3.4
1.3.5
1.3.6
1.3.7
1.4
Architectural Overview .......................................................................................... 36
Overview ...................................................................................................................... 36
Target Applications ........................................................................................................ 38
Features ....................................................................................................................... 38
ARM Cortex-M3 Processor Core .................................................................................... 38
On-Chip Memory ........................................................................................................... 40
Serial Communications Peripherals ................................................................................ 41
System Integration ........................................................................................................ 44
Analog .......................................................................................................................... 50
JTAG and ARM Serial Wire Debug ................................................................................ 51
Packaging and Temperature .......................................................................................... 52
Hardware Details .......................................................................................................... 52
2
2.1
2.2
2.2.1
2.2.2
2.2.3
2.2.4
2.3
2.3.1
2.3.2
2.3.3
2.3.4
2.3.5
2.3.6
2.4
2.4.1
2.4.2
2.4.3
2.4.4
2.4.5
2.4.6
2.4.7
2.5
2.5.1
2.5.2
2.5.3
2.5.4
The Cortex-M3 Processor ...................................................................................... 53
Block Diagram .............................................................................................................. 54
Overview ...................................................................................................................... 55
System-Level Interface .................................................................................................. 55
Integrated Configurable Debug ...................................................................................... 55
Trace Port Interface Unit (TPIU) ..................................................................................... 56
Cortex-M3 System Component Details ........................................................................... 56
Programming Model ...................................................................................................... 57
Processor Mode and Privilege Levels for Software Execution ........................................... 57
Stacks .......................................................................................................................... 57
Register Map ................................................................................................................ 58
Register Descriptions .................................................................................................... 59
Exceptions and Interrupts .............................................................................................. 72
Data Types ................................................................................................................... 72
Memory Model .............................................................................................................. 72
Memory Regions, Types and Attributes ........................................................................... 74
Memory System Ordering of Memory Accesses .............................................................. 74
Behavior of Memory Accesses ....................................................................................... 74
Software Ordering of Memory Accesses ......................................................................... 75
Bit-Banding ................................................................................................................... 76
Data Storage ................................................................................................................ 78
Synchronization Primitives ............................................................................................. 79
Exception Model ........................................................................................................... 80
Exception States ........................................................................................................... 81
Exception Types ............................................................................................................ 81
Exception Handlers ....................................................................................................... 84
Vector Table .................................................................................................................. 84
January 21, 2012
3
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