LM3S1N16 Datasheet, PDF (31/794 Pages) Texas Instruments – Stellaris® LM3S1N16 Microcontroller

Stellaris^® LM3S1N16 Microcontroller
Table 1. Revision History (continued)
Date
October 2009
Revision Description
6458 ■ Released new 1000, 3000, 5000 and 9000 series Stellaris^® devices.
■ The IDCODE value was corrected to be 0x4BA0.0477.
■ Clarified that the NMISET bit in the ICSR register in the NVIC is also a source for NMI.
■ Clarified the use of the LDO.
■ To clarify clock operation, reorganized clocking section, changed the USEFRACT bit to the DIV400
bit and the FRACT bit to the SYSDIV2LSB bit in the RCC2 register, added tables, and rewrote
descriptions.
■ Corrected bit description of the DSDIVORIDE field in the DSLPCLKCFG register.
■ Removed the DSFLASHCFG register at System Control offset 0x14C as it does not function correctly.
■ Removed the MAXADC1SPD and MAXADC0SPD fields from the DCGC0 as they have no function in
deep-sleep mode.
■ Corrected address offsets for the Flash Write Buffer (FWBn) registers.
■ Added Flash Control (FCTL) register at Internal memory offset 0x0F8 to help control frequent
power cycling when hibernation is not used.
■ Changed the name of the EPI channels for clarification: EPI0_TX became EPI0_WFIFO and EPI0_RX
became EPI0_NBRFIFO. This change was also made in the DC7 bit descriptions.
■ Removed the DMACHIS register at DMA module offset 0x504 as it does not function correctly.
■ Corrected alternate channel assignments for the µDMA controller.
■ Major improvements to the EPI chapter.
■ EPISDRAMCFG2 register was deleted as its function is not needed.
■ Clarified PWM source for ADC triggering
■ Changed SSI set up and hold times to be expressed in system clocks, not ns.
■ Updated Electrical Characteristics chapter with latest data. Changes were made to Hibernation,
ADC and EPI content.
■ Additional minor data sheet clarifications and corrections.
January 21, 2012
31
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