LM3S5737 Datasheet, PDF (727/833 Pages) Texas Instruments – Stellaris® LM3S5737 Microcontroller

Stellaris® LM3S5737 Microcontroller
Bit/Field
4
Name
FLUSH
Type
R/W
3
DATAERR / NAKTO R/W
2
ERROR
R/W
1
FULL
RO
Reset
0
Description
Flush FIFO
Value Description
0 No effect.
1 Flushes the next packet to be read from the endpoint receive
FIFO. The FIFO pointer is reset and the RXRDY bit is cleared.
Note that if the FIFO is double-buffered, FLUSH may have to be set
twice to completely clear the FIFO.
Important: ^{This bit should only be set when the RXRDY bit is set. At}
other times, it may cause data to be corrupted.
0
Data Error / NAK Timeout
Value Description
0 Normal operation.
1 Isochronous endpoints only: Indicates that RXRDY is set and
the data packet has a CRC or bit-stuff error. This bit is cleared
when RXRDY is cleared.
Bulk endpoints only: Indicates that the receive endpoint is halted
following the receipt of NAK responses for longer than the time
set by the NAKLMT field in the USBRXINTERVALn register.
Software must clear this bit to allow the endpoint to continue.
0
Error
Value Description
0 No error.
1 Three attempts have been made to receive a packet and no
data packet has been received. The EPn bit in the USBRXIS
register is set in this situation.
Software must clear this bit.
Note:
This bit is only valid when the receive endpoint is operating
in Bulk or Interrupt mode. In Isochronous mode, it always
returns zero.
0
FIFO Full
Value Description
0 The receive FIFO is not full.
1 No more packets can be loaded into the receive FIFO.
November 17, 2011
727
Texas Instruments-Production Data