LM3S5737 Datasheet, PDF (21/833 Pages) Texas Instruments – Stellaris® LM3S5737 Microcontroller

Stellaris® LM3S5737 Microcontroller
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Register 26:
UART Interrupt Clear (UARTICR), offset 0x044 ............................................................... 521
UART DMA Control (UARTDMACTL), offset 0x048 .......................................................... 523
UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0 ..................................... 524
UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4 ..................................... 525
UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8 ..................................... 526
UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC ..................................... 527
UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0 ...................................... 528
UART Peripheral Identification 1 (UARTPeriphID1), offset 0xFE4 ...................................... 529
UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8 ...................................... 530
UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC ..................................... 531
UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0 ........................................ 532
UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4 ........................................ 533
UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8 ........................................ 534
UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC ........................................ 535
Synchronous Serial Interface (SSI) ............................................................................................ 536
Register 1: SSI Control 0 (SSICR0), offset 0x000 .............................................................................. 550
Register 2: SSI Control 1 (SSICR1), offset 0x004 .............................................................................. 552
Register 3: SSI Data (SSIDR), offset 0x008 ...................................................................................... 554
Register 4: SSI Status (SSISR), offset 0x00C ................................................................................... 555
Register 5: SSI Clock Prescale (SSICPSR), offset 0x010 .................................................................. 557
Register 6: SSI Interrupt Mask (SSIIM), offset 0x014 ......................................................................... 558
Register 7: SSI Raw Interrupt Status (SSIRIS), offset 0x018 .............................................................. 560
Register 8: SSI Masked Interrupt Status (SSIMIS), offset 0x01C ........................................................ 561
Register 9: SSI Interrupt Clear (SSIICR), offset 0x020 ....................................................................... 562
Register 10: SSI DMA Control (SSIDMACTL), offset 0x024 ................................................................. 563
Register 11: SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0 ............................................. 564
Register 12: SSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4 ............................................. 565
Register 13: SSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8 ............................................. 566
Register 14: SSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC ............................................ 567
Register 15: SSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0 ............................................. 568
Register 16: SSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4 ............................................. 569
Register 17: SSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8 ............................................. 570
Register 18: SSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC ............................................ 571
Register 19: SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0 ............................................... 572
Register 20: SSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4 ............................................... 573
Register 21: SSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8 ............................................... 574
Register 22: SSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC ............................................... 575
Inter-Integrated Circuit (I²C) Interface ........................................................................................ 576
Register 1: I²C Master Slave Address (I2CMSA), offset 0x000 ........................................................... 592
Register 2: I²C Master Control/Status (I2CMCS), offset 0x004 ........................................................... 593
Register 3: I²C Master Data (I2CMDR), offset 0x008 ......................................................................... 597
Register 4: I²C Master Timer Period (I2CMTPR), offset 0x00C ........................................................... 598
Register 5: I²C Master Interrupt Mask (I2CMIMR), offset 0x010 ......................................................... 599
Register 6: I²C Master Raw Interrupt Status (I2CMRIS), offset 0x014 ................................................. 600
Register 7: I²C Master Masked Interrupt Status (I2CMMIS), offset 0x018 ........................................... 601
Register 8: I²C Master Interrupt Clear (I2CMICR), offset 0x01C ......................................................... 602
Register 9: I²C Master Configuration (I2CMCR), offset 0x020 ............................................................ 603
November 17, 2011
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