LM3S5737 Datasheet, PDF (17/833 Pages) Texas Instruments – Stellaris® LM3S5737 Microcontroller

Stellaris® LM3S5737 Microcontroller
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Register 34:
Device Capabilities 4 (DC4), offset 0x01C ....................................................................... 210
Device Capabilities 5 (DC5), offset 0x020 ........................................................................ 211
Device Capabilities 6 (DC6), offset 0x024 ........................................................................ 212
Device Capabilities 7 (DC7), offset 0x028 ........................................................................ 213
Run Mode Clock Gating Control Register 0 (RCGC0), offset 0x100 ................................... 215
Sleep Mode Clock Gating Control Register 0 (SCGC0), offset 0x110 ................................. 217
Deep Sleep Mode Clock Gating Control Register 0 (DCGC0), offset 0x120 ....................... 219
Run Mode Clock Gating Control Register 1 (RCGC1), offset 0x104 ................................... 221
Sleep Mode Clock Gating Control Register 1 (SCGC1), offset 0x114 ................................. 223
Deep Sleep Mode Clock Gating Control Register 1 (DCGC1), offset 0x124 ....................... 225
Run Mode Clock Gating Control Register 2 (RCGC2), offset 0x108 ................................... 227
Sleep Mode Clock Gating Control Register 2 (SCGC2), offset 0x118 ................................. 229
Deep Sleep Mode Clock Gating Control Register 2 (DCGC2), offset 0x128 ....................... 231
Software Reset Control 0 (SRCR0), offset 0x040 ............................................................. 233
Software Reset Control 1 (SRCR1), offset 0x044 ............................................................. 234
Software Reset Control 2 (SRCR2), offset 0x048 ............................................................. 235
Hibernation Module ..................................................................................................................... 236
Register 1: Hibernation RTC Counter (HIBRTCC), offset 0x000 ......................................................... 245
Register 2: Hibernation RTC Match 0 (HIBRTCM0), offset 0x004 ....................................................... 246
Register 3: Hibernation RTC Match 1 (HIBRTCM1), offset 0x008 ....................................................... 247
Register 4: Hibernation RTC Load (HIBRTCLD), offset 0x00C ........................................................... 248
Register 5: Hibernation Control (HIBCTL), offset 0x010 ..................................................................... 249
Register 6: Hibernation Interrupt Mask (HIBIM), offset 0x014 ............................................................. 252
Register 7: Hibernation Raw Interrupt Status (HIBRIS), offset 0x018 .................................................. 253
Register 8: Hibernation Masked Interrupt Status (HIBMIS), offset 0x01C ............................................ 254
Register 9: Hibernation Interrupt Clear (HIBIC), offset 0x020 ............................................................. 255
Register 10: Hibernation RTC Trim (HIBRTCT), offset 0x024 ............................................................... 256
Register 11: Hibernation Data (HIBDATA), offset 0x030-0x12C ............................................................ 257
Internal Memory ........................................................................................................................... 258
Register 1: ROM Control (RMCTL), offset 0x0F0 .............................................................................. 264
Register 2: Flash Memory Address (FMA), offset 0x000 .................................................................... 265
Register 3: Flash Memory Data (FMD), offset 0x004 ......................................................................... 266
Register 4: Flash Memory Control (FMC), offset 0x008 ..................................................................... 267
Register 5: Flash Controller Raw Interrupt Status (FCRIS), offset 0x00C ............................................ 269
Register 6: Flash Controller Interrupt Mask (FCIM), offset 0x010 ........................................................ 270
Register 7: Flash Controller Masked Interrupt Status and Clear (FCMISC), offset 0x014 ..................... 271
Register 8: USec Reload (USECRL), offset 0x140 ............................................................................ 273
Register 9: Flash Memory Protection Read Enable 0 (FMPRE0), offset 0x130 and 0x200 ................... 274
Register 10: Flash Memory Protection Program Enable 0 (FMPPE0), offset 0x134 and 0x400 ............... 275
Register 11: User Debug (USER_DBG), offset 0x1D0 ......................................................................... 276
Register 12: User Register 0 (USER_REG0), offset 0x1E0 .................................................................. 277
Register 13: User Register 1 (USER_REG1), offset 0x1E4 .................................................................. 278
Register 14: User Register 2 (USER_REG2), offset 0x1E8 .................................................................. 279
Register 15: User Register 3 (USER_REG3), offset 0x1EC ................................................................. 280
Register 16: Flash Memory Protection Read Enable 1 (FMPRE1), offset 0x204 .................................... 281
Register 17: Flash Memory Protection Read Enable 2 (FMPRE2), offset 0x208 .................................... 282
Register 18: Flash Memory Protection Read Enable 3 (FMPRE3), offset 0x20C ................................... 283
Register 19: Flash Memory Protection Program Enable 1 (FMPPE1), offset 0x404 ............................... 284
November 17, 2011
17
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