LM3S5737 Datasheet, PDF (381/833 Pages) Texas Instruments – Stellaris® LM3S5737 Microcontroller

Stellaris® LM3S5737 Microcontroller
Register 18: GPIO Digital Enable (GPIODEN), offset 0x51C
Note: Pins configured as digital inputs are Schmitt-triggered.
The GPIODEN register is the digital enable register. By default, with the exception of the GPIO
signals used for JTAG/SWD function, all other GPIO signals are configured out of reset to be undriven
(tristate). Their digital function is disabled; they do not drive a logic value on the pin and they do not
allow the pin voltage into the GPIO receiver. To use the pin in a digital function (either GPIO or
alternate function), the corresponding GPIODEN bit must be set.
Note:
The GPIO commit control registers provide a layer of protection against accidental
programming of critical hardware peripherals. Protection is currently provided for the NMI
pin (PB7) and the four JTAG/SWD pins (PC[3:0]). Writes to protected bits of the GPIO
Alternate Function Select (GPIOAFSEL) register (see page 371), GPIO Pull-Up Select
(GPIOPUR) register (see page 377), and GPIO Digital Enable (GPIODEN) register (see
page 381) are not committed to storage unless the GPIO Lock (GPIOLOCK) register (see
page 383) has been unlocked and the appropriate bits of the GPIO Commit (GPIOCR)
register (see page 384) have been set to 1.
GPIO Digital Enable (GPIODEN)
GPIO Port A (APB) base: 0x4000.4000
GPIO Port A (AHB) base: 0x4005.8000
GPIO Port B (APB) base: 0x4000.5000
GPIO Port B (AHB) base: 0x4005.9000
GPIO Port C (APB) base: 0x4000.6000
GPIO Port C (AHB) base: 0x4005.A000
GPIO Port D (APB) base: 0x4000.7000
GPIO Port D (AHB) base: 0x4005.B000
GPIO Port E (APB) base: 0x4002.4000
GPIO Port E (AHB) base: 0x4005.C000
GPIO Port F (APB) base: 0x4002.5000
GPIO Port F (AHB) base: 0x4005.D000
GPIO Port G (APB) base: 0x4002.6000
GPIO Port G (AHB) base: 0x4005.E000
GPIO Port H (APB) base: 0x4002.7000
GPIO Port H (AHB) base: 0x4005.F000
Offset 0x51C
Type R/W, reset -
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
DEN
Type RO
RO
RO
RO
RO
RO
RO
RO
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
-
-
-
-
-
-
-
-
Bit/Field
31:8
Name
reserved
Type
RO
Reset
0x00
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
November 17, 2011
381
Texas Instruments-Production Data