LM3S5737 Datasheet, PDF (238/833 Pages) Texas Instruments – Stellaris® LM3S5737 Microcontroller

Hibernation Module
6.3
6.3.1
6.3.2
Functional Description
The Hibernation module controls the power to the processor with an enable signal (HIB) that signals
an external voltage regulator to turn off.
The Hibernation module power source is determined dynamically. The supply voltage of the
Hibernation module is the larger of the main voltage source (V_DD) or the battery/auxilliary voltage
source (V_BAT). A voting circuit indicates the larger and an internal power switch selects the appropriate
voltage source. The Hibernation module also has a separate clock source to maintain a real-time
clock (RTC). Once in hibernation, the module signals an external voltage regulator to turn back on
the power when an external pin (WAKE) is asserted, or when the internal RTC reaches a certain
value. The Hibernation module can also detect when the battery voltage is low, and optionally
prevent hibernation when this occurs.
When waking from hibernation, the HIB signal is deasserted. The return of V_DD causes a POR to
be executed. The time from when the WAKE signal is asserted to when code begins execution is
equal to the wake-up time (t_{WAKE_TO_HIB}) plus the power-on reset time (T_IRPOR).
Register Access Timing
Because the Hibernation module has an independent clocking domain, certain registers must be
written only with a timing gap between accesses. The delay time is t_{HIB_REG_WRITE}, therefore software
must guarantee that a delay of t_{HIB_REG_WRITE} is inserted between back-to-back writes to certain
Hibernation registers, or between a write followed by a read to those same registers. There is no
restriction on timing for back-to-back reads from the Hibernation module. Software may make use
of the WRC bit in the HIBCTL register to ensure that the required timing gap has elapsed. This bit is
cleared on a write operation and set once the write completes, indicating to software that another
write or read may be started safely. Software should poll HIBCTL for WRC=1 prior to accessing any
affected register. The following registers are subject to this timing restriction:
■ Hibernation RTC Counter (HIBRTCC)
■ Hibernation RTC Match 0 (HIBRTCM0)
■ Hibernation RTC Match 1 (HIBRTCM1)
■ Hibernation RTC Load (HIBRTCLD)
■ Hibernation RTC Trim (HIBRTCT)
■ Hibernation Data (HIBDATA)
Clock Source
The Hibernation module must be clocked by an external source, even if the RTC feature is not used.
An external oscillator or crystal can be used for this purpose. To use a crystal, a 4.194304-MHz
crystal is connected to the XOSC0 and XOSC1 pins. This clock signal is divided by 128 internally to
produce the 32.768-kHz clock reference. For an alternate clock source, a 32.768-kHz oscillator can
be connected to the XOSC0 pin. See Figure 6-2 on page 239 and Figure 6-3 on page 239. Note that
these diagrams only show the connection to the Hibernation pins and not to the full system. See
“Hibernation Module” on page 777 for specific values.
The clock source is enabled by setting the CLK32EN bit of the HIBCTL register. The type of clock
source is selected by setting the CLKSEL bit to 0 for a 4.194304-MHz clock source, and to 1 for a
32.768-kHz clock source. If the bit is set to 0, the 4.194304-MHz input clock is divided by 128,
238
November 17, 2011
Texas Instruments-Production Data