LM3S5737 Datasheet, PDF (147/833 Pages) Texas Instruments – Stellaris® LM3S5737 Microcontroller

Stellaris® LM3S5737 Microcontroller
Register 40: Bus Fault Address (FAULTADDR), offset 0xD38
Note: This register can only be accessed from privileged mode.
The FAULTADDR register contains the address of the location that generated a bus fault. When
an unaligned access faults, the address in the FAULTADDR register is the one requested by the
instruction, even if it is not the address of the fault. Bits in the Bus Fault Status (BFAULTSTAT)
register indicate the cause of the fault and whether the value in the FAULTADDR register is valid
(see page 139).
Bus Fault Address (FAULTADDR)
Base 0xE000.E000
Offset 0xD38
Type R/W, reset -
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
ADDR
Type R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ADDR
Type R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Bit/Field
31:0
Name
ADDR
Type
R/W
Reset
-
Description
Fault Address
When the FAULTADDRV bit of BFAULTSTAT is set, this field holds the
address of the location that generated the bus fault.
3.6 Memory Protection Unit (MPU) Register Descriptions
This section lists and describes the Memory Protection Unit (MPU) registers, in numerical order by
address offset.
The MPU registers can only be accessed from privileged mode.
November 17, 2011
147
Texas Instruments-Production Data