LM3S5737 Datasheet, PDF (192/833 Pages) Texas Instruments – Stellaris® LM3S5737 Microcontroller

System Control
Register 8: Run-Mode Clock Configuration (RCC), offset 0x060
This register is defined to provide source control and frequency speed.
Run-Mode Clock Configuration (RCC)
Base 0x400F.E000
Offset 0x060
Type R/W, reset 0x0780.3AD1
31
30
29
28
27
26
reserved
ACG
Type RO
RO
RO
RO
R/W
R/W
Reset
0
0
0
0
0
1
Type
Reset
15
14
reserved
RO
RO
0
0
13
12
11
PWRDN reserved BYPASS
R/W
RO
R/W
1
1
1
10
R/W
0
25
24
SYSDIV
R/W
R/W
1
1
9
8
XTAL
R/W
R/W
1
0
23
22
21
20
USESYSDIV
R/W
R/W
RO
RO
1
0
0
0
7
6
5
4
OSCSRC
R/W
R/W
R/W
R/W
1
1
0
1
19
18
17
16
reserved
RO
RO
RO
RO
0
0
0
0
3
2
reserved
RO
RO
0
0
1
0
IOSCDIS MOSCDIS
R/W
R/W
0
1
Bit/Field
31:28
27
26:23
22
Name
reserved
ACG
SYSDIV
USESYSDIV
Type
RO
R/W
R/W
R/W
Reset
0x0
0
0xF
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Auto Clock Gating
This bit specifies whether the system uses the Sleep-Mode Clock
Gating Control (SCGCn) registers and Deep-Sleep-Mode Clock
Gating Control (DCGCn) registers if the controller enters a Sleep or
Deep-Sleep mode (respectively). If set, the SCGCn or DCGCn registers
are used to control the clocks distributed to the peripherals when the
controller is in a sleep mode. Otherwise, the Run-Mode Clock Gating
Control (RCGCn) registers are used when the controller enters a sleep
mode.
The RCGCn registers are always used to control the clocks in Run
mode.
This allows peripherals to consume less power when the controller is
in a sleep mode and the peripheral is unused.
System Clock Divisor
Specifies which divisor is used to generate the system clock from either
the PLL output or the oscillator source (depending on how the BYPASS
bit in this register is configured). See Table 5-4 on page 177 for bit
encodings.
If the SYSDIV value is less than MINSYSDIV (see page 206), and the
PLL is being used, then the MINSYSDIV value is used as the divisor.
If the PLL is not being used, the SYSDIV value can be less than
MINSYSDIV.
Enable System Clock Divider
Use the system clock divider as the source for the system clock. The
system clock divider is forced to be used when the PLL is selected as
the source.
If the USERCC2 bit in the RCC2 register is set, then the SYSDIV2 field
in the RCC2 register is used as the system clock divider rather than the
SYSDIV field in this register.
192
November 17, 2011
Texas Instruments-Production Data