LM3S5737 Datasheet, PDF (668/833 Pages) Texas Instruments – Stellaris® LM3S5737 Microcontroller

Universal Serial Bus (USB) Controller
retries the transaction. If after three attempts the target Device has still not responded, the USB
Host controller clears the REQPKT bit and sets the ERROR bit in the USBCSRL0 register.
17.3.2.3
OUT Transactions as a Host
OUT transactions are handled in a similar manner to the way in which IN transactions are handled
when the USB controller is in Device mode. The TXRDY bit in the USBTXCSRLn register must be
set as each packet is loaded into the transmit FIFO. Again, setting the AUTOSET bit in the
USBTXCSRHn register automatically sets TXRDY when a maximum-sized packet has been loaded
into the FIFO. Furthermore, AUTOSET can be used with the µDMA controller to perform complete
bulk transfers without software intervention.
If the target Device responds to the OUT token with a NAK, the USB Host controller keeps retrying
the transaction until the NAK Limit that has been set has been reached. However, if the target Device
responds with a STALL, the USB controller does not retry the transaction but interrupts the main
processor by setting the STALLED bit in the USBTXCSRLn register. If the target Device does not
respond to the OUT token within the required time, or the packet contained a CRC or bit-stuff error,
the USB Host controller retries the transaction. If after three attempts the target Device has still not
responded, the USB controller flushes the FIFO and sets the ERROR bit in the USBTXCSRLn register.
17.3.2.4
Transaction Scheduling
Scheduling of transactions is handled automatically by the USB Host controller. The Host controller
allows configuration of the endpoint communication scheduling based on the type of endpoint
transaction. Interrupt transactions can be scheduled to occur in the range of every frame to every
255 frames in 1 frame increments. Bulk endpoints do not allow scheduling parameters, but do allow
for a NAK timeout in the event an endpoint on a Device is not responding. Isochronous endpoints
can be scheduled from every frame to every 2¹⁶ frames, in powers of 2.
The USB controller maintains a frame counter. If the target Device is a full-speed device, the USB
controller automatically sends an SOF packet at the start of each frame and increments the frame
counter. If the target Device is a low-speed device, a K state is transmitted on the bus to act as a
keep-alive to stop the low-speed device from going into SUSPEND mode.
After the SOF packet has been transmitted, the USB Host controller cycles through all the configured
endpoints looking for active transactions. An active transaction is defined as a receive endpoint for
which the REQPKT bit is set or a transmit endpoint for which the TXRDY bit and/or the FIFONE bit is
set.
An isochronous or interrupt transaction is started if the transaction is found on the first scheduler
cycle of a frame and if the interval counter for that endpoint has counted down to zero. As a result,
only one interrupt or isochronous transaction occurs per endpoint every n frames, where n is the
interval set via the USB Host Transmit Interval Endpoint n (USBTXINTERVALn) or USB Host
Receive Interval Endpoint n (USBRXINTERVALn) register for that endpoint.
An active bulk transaction starts immediately, provided sufficient time is left in the frame to complete
the transaction before the next SOF packet is due. If the transaction must be retried (for example,
because a NAK was received or the target Device did not respond), then the transaction is not
retried until the transaction scheduler has first checked all the other endpoints for active transactions.
This process ensures that an endpoint that is sending a lot of NAKs does not block other transactions
on the bus. The controller also allows the user to specify a limit to the length of time for NAKs to be
received from a target Device before the endpoint times out.
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November 17, 2011
Texas Instruments-Production Data