LM3S5737 Datasheet, PDF (12/833 Pages) Texas Instruments – Stellaris® LM3S5737 Microcontroller

Table of Contents
List of Tables
Table 1.
Table 2.
Table 2-1.
Table 2-2.
Table 2-3.
Table 2-4.
Table 2-5.
Table 2-6.
Table 2-7.
Table 2-8.
Table 2-9.
Table 2-10.
Table 2-11.
Table 2-12.
Table 2-13.
Table 3-1.
Table 3-2.
Table 3-3.
Table 3-4.
Table 3-5.
Table 3-6.
Table 3-7.
Table 3-8.
Table 3-9.
Table 4-1.
Table 4-2.
Table 4-3.
Table 5-1.
Table 5-2.
Table 5-3.
Table 5-4.
Table 5-5.
Table 5-6.
Table 5-7.
Table 6-1.
Table 6-2.
Table 7-1.
Table 7-2.
Table 7-3.
Table 8-1.
Table 8-2.
Table 8-3.
Table 8-4.
Table 8-5.
Table 8-6.
Table 8-7.
Revision History .................................................................................................. 25
Documentation Conventions ................................................................................ 32
Summary of Processor Mode, Privilege Level, and Stack Use ................................ 56
Processor Register Map ....................................................................................... 57
PSR Register Combinations ................................................................................. 62
Memory Map ....................................................................................................... 70
Memory Access Behavior ..................................................................................... 73
SRAM Memory Bit-Banding Regions .................................................................... 75
Peripheral Memory Bit-Banding Regions ............................................................... 75
Exception Types .................................................................................................. 80
Interrupts ............................................................................................................ 81
Exception Return Behavior ................................................................................... 86
Faults ................................................................................................................. 87
Fault Status and Fault Address Registers .............................................................. 88
Cortex-M3 Instruction Summary ........................................................................... 90
Core Peripheral Register Regions ......................................................................... 93
Memory Attributes Summary ................................................................................ 96
TEX, S, C, and B Bit Field Encoding ..................................................................... 99
Cache Policy for Memory Attribute Encoding ....................................................... 100
AP Bit Field Encoding ........................................................................................ 100
Memory Region Attributes for Stellaris Microcontrollers ........................................ 100
Peripherals Register Map ................................................................................... 101
Interrupt Priority Levels ...................................................................................... 126
Example SIZE Field Values ................................................................................ 154
JTAG_SWD_SWO Signals (100LQFP) ................................................................ 158
JTAG Port Pins Reset State ............................................................................... 159
JTAG Instruction Register Commands ................................................................. 165
System Control & Clocks Signals (100LQFP) ...................................................... 169
Reset Sources ................................................................................................... 170
Clock Source Options ........................................................................................ 175
Possible System Clock Frequencies Using the SYSDIV Field ............................... 177
Examples of Possible System Clock Frequencies Using the SYSDIV2 Field .......... 177
System Control Register Map ............................................................................. 181
RCC2 Fields that Override RCC fields ................................................................. 199
Hibernate Signals (100LQFP) ............................................................................. 237
Hibernation Module Register Map ....................................................................... 243
Flash Protection Policy Combinations ................................................................. 260
User-Programmable Flash Memory Resident Registers ....................................... 262
Flash Register Map ............................................................................................ 262
DMA Channel Assignments ............................................................................... 289
Request Type Support ....................................................................................... 290
Control Structure Memory Map ........................................................................... 291
Channel Control Structure .................................................................................. 291
μDMA Read Example: 8-Bit Peripheral ................................................................ 300
μDMA Interrupt Assignments .............................................................................. 301
Channel Control Structure Offsets for Channel 30 ................................................ 302
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November 17, 2011
Texas Instruments-Production Data