LM3S5737 Datasheet, PDF (402/833 Pages) Texas Instruments – Stellaris® LM3S5737 Microcontroller

General-Purpose Timers
pin placements for these GP Timer signals. The AFSEL bit in the GPIO Alternate Function Select
(GPIOAFSEL) register (page 371) should be set to choose the GP Timer function. For more information
on configuring GPIOs, see “General-Purpose Input/Outputs (GPIOs)” on page 348.
Table 10-2. General-Purpose Timers Signals (100LQFP)
Pin Name
Pin Number Pin Type Buffer Type^a Description
CCP0
66
I/O
TTL
Capture/Compare/PWM 0.
CCP1
67
I/O
TTL
Capture/Compare/PWM 1.
CCP2
91
I/O
TTL
Capture/Compare/PWM 2.
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
10.3
Functional Description
The main components of each GPTM block are two free-running 16-bit up/down counters (referred
to as TimerA and TimerB), two 16-bit match registers, and two 16-bit load/initialization registers and
their associated control functions. The exact functionality of each GPTM is controlled by software
and configured through the register interface.
Software configures the GPTM using the GPTM Configuration (GPTMCFG) register (see page 412),
the GPTM TimerA Mode (GPTMTAMR) register (see page 413), and the GPTM TimerB Mode
(GPTMTBMR) register (see page 415). When in one of the 32-bit modes, the timer can only act as
a 32-bit timer. However, when configured in 16-bit mode, the GPTM can have its two 16-bit timers
configured in any combination of the 16-bit modes.
10.3.1
GPTM Reset Conditions
After reset has been applied to the GPTM module, the module is in an inactive state, and all control
registers are cleared and in their default states. Counters TimerA and TimerB are initialized to
0xFFFF, along with their corresponding load registers: the GPTM TimerA Interval Load
(GPTMTAILR) register (see page 426) and the GPTM TimerB Interval Load (GPTMTBILR) register
(see page 427). The prescale counters are initialized to 0x00: the GPTM TimerA Prescale
(GPTMTAPR) register (see page 430) and the GPTM TimerB Prescale (GPTMTBPR) register (see
page 431).
10.3.2
32-Bit Timer Operating Modes
This section describes the three GPTM 32-bit timer modes (One-Shot, Periodic, and RTC) and their
configuration.
The GPTM is placed into 32-bit mode by writing a 0 (One-Shot/Periodic 32-bit timer mode) or a 1
(RTC mode) to the GPTM Configuration (GPTMCFG) register. In both configurations, certain GPTM
registers are concatenated to form pseudo 32-bit registers. These registers include:
■ GPTM TimerA Interval Load (GPTMTAILR) register [15:0], see page 426
■ GPTM TimerB Interval Load (GPTMTBILR) register [15:0], see page 427
■ GPTM TimerA (GPTMTAR) register [15:0], see page 432
■ GPTM TimerB (GPTMTBR) register [15:0], see page 433
In the 32-bit modes, the GPTM translates a 32-bit write access to GPTMTAILR into a write access
to both GPTMTAILR and GPTMTBILR. The resulting word ordering for such a write operation is:
402
November 17, 2011
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