LM3S5737 Datasheet, PDF (301/833 Pages) Texas Instruments – Stellaris® LM3S5737 Microcontroller

Stellaris® LM3S5737 Microcontroller
8.2.10
8.3
8.3.1
8.3.2
8.3.2.1
channel may be used for software requests as long as the corresponding peripheral is not using
μDMA.
Interrupts and Errors
When a DMA transfer is complete, the μDMA controller will generate a completion interrupt on the
interrupt vector of the peripheral. If the transfer uses the software DMA channel, then the completion
interrupt will occur on the dedicated software DMA interrupt vector.
If the μDMA controller encounters a bus or memory protection error as it attempts to perform a data
transfer, it will disable the DMA channel that caused the error, and generate an interrupt on the
μDMA Error interrupt vector. The processor can read the DMA Bus Error Clear (DMAERRCLR)
register to determine if an error is pending. The ERRCLR bit will be set if an error occurred. The error
can be cleared by writing a 1 to the ERRCLR bit.
If the peripheral generates an error that causes an interrupt, the interrupt will be generated on the
interrupt vector for that peripheral. This is the same whether or not μDMA is being used with the
peripheral.
Table 8-6 on page 301 shows the dedicated interrupt assignments for the μDMA controller.
Table 8-6. μDMA Interrupt Assignments
Interrupt
46
47
Assignment
μDMA Software Channel Transfer
μDMA Error
Initialization and Configuration
Module Initialization
Before the μDMA controller can be used, it must be enabled in the System Control block and in the
peripheral. The location of the channel control structure must also be programmed.
The following steps should be performed one time during system initialization:
1. The μDMA peripheral must be enabled in the System Control block. To do this, set the UDMA
bit of the System Control RCGC2 register.
2. Enable the μDMA controller by setting the MASTEREN bit of the DMA Configuration (DMACFG)
register.
3. Program the location of the channel control table by writing the base address of the table to the
DMA Channel Control Base Pointer (DMACTLBASE) register. The base address must be
aligned on a 1024-byte boundary.
Configuring a Memory-to-Memory Transfer
μDMA channel 30 is dedicated for software-initiated transfers. However, any channel can be used
for software-initiated, memory-to-memory transfer if the associated peripheral is not being used.
Configure the Channel Attributes
First, configure the channel attributes:
1. Set bit 30 of the DMA Channel Priority Set (DMAPRIOSET) or DMA Channel Priority Clear
(DMAPRIOCLR) registers to set the channel to High priority or Default priority.
November 17, 2011
301
Texas Instruments-Production Data