LM3S5737 Datasheet, PDF (18/833 Pages) Texas Instruments – Stellaris® LM3S5737 Microcontroller

Table of Contents
Register 20: Flash Memory Protection Program Enable 2 (FMPPE2), offset 0x408 ............................... 285
Register 21: Flash Memory Protection Program Enable 3 (FMPPE3), offset 0x40C ............................... 286
Micro Direct Memory Access (μDMA) ........................................................................................ 287
Register 1: DMA Channel Source Address End Pointer (DMASRCENDP), offset 0x000 ...................... 309
Register 2: DMA Channel Destination Address End Pointer (DMADSTENDP), offset 0x004 ................ 310
Register 3: DMA Channel Control Word (DMACHCTL), offset 0x008 .................................................. 311
Register 4: DMA Status (DMASTAT), offset 0x000 ............................................................................ 315
Register 5: DMA Configuration (DMACFG), offset 0x004 ................................................................... 317
Register 6: DMA Channel Control Base Pointer (DMACTLBASE), offset 0x008 .................................. 318
Register 7: DMA Alternate Channel Control Base Pointer (DMAALTBASE), offset 0x00C .................... 319
Register 8: DMA Channel Wait on Request Status (DMAWAITSTAT), offset 0x010 ............................. 320
Register 9: DMA Channel Software Request (DMASWREQ), offset 0x014 ......................................... 321
Register 10: DMA Channel Useburst Set (DMAUSEBURSTSET), offset 0x018 .................................... 322
Register 11: DMA Channel Useburst Clear (DMAUSEBURSTCLR), offset 0x01C ................................. 324
Register 12: DMA Channel Request Mask Set (DMAREQMASKSET), offset 0x020 .............................. 325
Register 13: DMA Channel Request Mask Clear (DMAREQMASKCLR), offset 0x024 ........................... 327
Register 14: DMA Channel Enable Set (DMAENASET), offset 0x028 ................................................... 328
Register 15: DMA Channel Enable Clear (DMAENACLR), offset 0x02C ............................................... 330
Register 16: DMA Channel Primary Alternate Set (DMAALTSET), offset 0x030 .................................... 331
Register 17: DMA Channel Primary Alternate Clear (DMAALTCLR), offset 0x034 ................................. 333
Register 18: DMA Channel Priority Set (DMAPRIOSET), offset 0x038 ................................................. 334
Register 19: DMA Channel Priority Clear (DMAPRIOCLR), offset 0x03C .............................................. 336
Register 20: DMA Bus Error Clear (DMAERRCLR), offset 0x04C ........................................................ 337
Register 21: DMA Peripheral Identification 0 (DMAPeriphID0), offset 0xFE0 ......................................... 339
Register 22: DMA Peripheral Identification 1 (DMAPeriphID1), offset 0xFE4 ......................................... 340
Register 23: DMA Peripheral Identification 2 (DMAPeriphID2), offset 0xFE8 ......................................... 341
Register 24: DMA Peripheral Identification 3 (DMAPeriphID3), offset 0xFEC ........................................ 342
Register 25: DMA Peripheral Identification 4 (DMAPeriphID4), offset 0xFD0 ......................................... 343
Register 26: DMA PrimeCell Identification 0 (DMAPCellID0), offset 0xFF0 ........................................... 344
Register 27: DMA PrimeCell Identification 1 (DMAPCellID1), offset 0xFF4 ........................................... 345
Register 28: DMA PrimeCell Identification 2 (DMAPCellID2), offset 0xFF8 ........................................... 346
Register 29: DMA PrimeCell Identification 3 (DMAPCellID3), offset 0xFFC ........................................... 347
General-Purpose Input/Outputs (GPIOs) ................................................................................... 348
Register 1: GPIO Data (GPIODATA), offset 0x000 ............................................................................ 361
Register 2: GPIO Direction (GPIODIR), offset 0x400 ......................................................................... 362
Register 3: GPIO Interrupt Sense (GPIOIS), offset 0x404 .................................................................. 363
Register 4: GPIO Interrupt Both Edges (GPIOIBE), offset 0x408 ........................................................ 364
Register 5: GPIO Interrupt Event (GPIOIEV), offset 0x40C ................................................................ 365
Register 6: GPIO Interrupt Mask (GPIOIM), offset 0x410 ................................................................... 366
Register 7: GPIO Raw Interrupt Status (GPIORIS), offset 0x414 ........................................................ 367
Register 8: GPIO Masked Interrupt Status (GPIOMIS), offset 0x418 ................................................... 368
Register 9: GPIO Interrupt Clear (GPIOICR), offset 0x41C ................................................................ 370
Register 10: GPIO Alternate Function Select (GPIOAFSEL), offset 0x420 ............................................ 371
Register 11: GPIO 2-mA Drive Select (GPIODR2R), offset 0x500 ........................................................ 373
Register 12: GPIO 4-mA Drive Select (GPIODR4R), offset 0x504 ........................................................ 374
Register 13: GPIO 8-mA Drive Select (GPIODR8R), offset 0x508 ........................................................ 375
Register 14: GPIO Open Drain Select (GPIOODR), offset 0x50C ......................................................... 376
Register 15: GPIO Pull-Up Select (GPIOPUR), offset 0x510 ................................................................ 377
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November 17, 2011
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