LM3S5737 Datasheet, PDF (717/833 Pages) Texas Instruments – Stellaris® LM3S5737 Microcontroller

Stellaris® LM3S5737 Microcontroller
Register 53: USB Transmit Control and Status Endpoint 1 Low (USBTXCSRL1),
offset 0x112
Register 54: USB Transmit Control and Status Endpoint 2 Low (USBTXCSRL2),
offset 0x122
Register 55: USB Transmit Control and Status Endpoint 3 Low (USBTXCSRL3),
offset 0x132
Host
USBTXCSRLn is an 8-bit register that provides control and status bits for transfers through the
currently selected transmit endpoint.
Device
Host Mode
USB Transmit Control and Status Endpoint 1 Low (USBTXCSRL1)
Base 0x4005.0000
Offset 0x112
Type R/W, reset 0x00
7
6
5
4
3
2
1
0
NAKTO CLRDT STALLED SETUP FLUSH ERROR FIFONE TXRDY
Type R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit/Field
7
Name
NAKTO
Type
R/W
Reset
0
Description
NAK Timeout
Value Description
0 No timeout.
1 Bulk endpoints only: Indicates that the transmit endpoint is halted
following the receipt of NAK responses for longer than the time
set by the NAKLMT field in the USBTXINTERVALn register.
Software must clear this bit to allow the endpoint to continue.
6
CLRDT
R/W
0
Clear Data Toggle
Writing a 1 to this bit clears the DT bit in the USBTXCSRHn register.
5
STALLED
R/W
0
Endpoint Stalled
Value Description
0 A STALL handshake has not been received.
1 Indicates that a STALL handshake has been received. When
this bit is set, any µDMA request that is in progress is stopped,
the FIFO is completely flushed, and the TXRDY bit is cleared.
Software must clear this bit.
November 17, 2011
717
Texas Instruments-Production Data