LM3S5737 Datasheet, PDF (11/833 Pages) Texas Instruments – Stellaris® LM3S5737 Microcontroller

Stellaris® LM3S5737 Microcontroller
Figure 14-2. TI Synchronous Serial Frame Format (Single Transfer) ........................................ 540
Figure 14-3. TI Synchronous Serial Frame Format (Continuous Transfer) ................................ 541
Figure 14-4. Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 .......................... 541
Figure 14-5. Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 .................. 542
Figure 14-6. Freescale SPI Frame Format with SPO=0 and SPH=1 ......................................... 543
Figure 14-7. Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 ............... 543
Figure 14-8. Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 ........ 544
Figure 14-9. Freescale SPI Frame Format with SPO=1 and SPH=1 ......................................... 545
Figure 14-10. MICROWIRE Frame Format (Single Frame) ........................................................ 545
Figure 14-11. MICROWIRE Frame Format (Continuous Transfer) ............................................. 546
Figure 14-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements ............ 547
Figure 15-1. I²C Block Diagram ............................................................................................. 577
Figure 15-2. I²C Bus Configuration ........................................................................................ 578
Figure 15-3. START and STOP Conditions ............................................................................. 578
Figure 15-4. Complete Data Transfer with a 7-Bit Address ....................................................... 579
Figure 15-5. R/S Bit in First Byte ............................................................................................ 579
Figure 15-6. Data Validity During Bit Transfer on the I²C Bus ................................................... 579
Figure 15-7. Master Single SEND .......................................................................................... 583
Figure 15-8. Master Single RECEIVE ..................................................................................... 584
Figure 15-9. Master Burst SEND ........................................................................................... 585
Figure 15-10. Master Burst RECEIVE ...................................................................................... 586
Figure 15-11. Master Burst RECEIVE after Burst SEND ............................................................ 587
Figure 15-12. Master Burst SEND after Burst RECEIVE ............................................................ 588
Figure 15-13. Slave Command Sequence ................................................................................ 589
Figure 16-1. CAN Controller Block Diagram ............................................................................ 614
Figure 16-2. CAN Data/Remote Frame .................................................................................. 615
Figure 16-3. Message Objects in a FIFO Buffer ...................................................................... 623
Figure 16-4. CAN Bit Time .................................................................................................... 627
Figure 17-1. USB Module Block Diagram ............................................................................... 660
Figure 18-1. 100-Pin LQFP Package Pin Diagram .................................................................. 753
Figure 21-1. Load Conditions ................................................................................................ 772
Figure 21-2. JTAG Test Clock Input Timing ............................................................................. 775
Figure 21-3. JTAG Test Access Port (TAP) Timing .................................................................. 775
Figure 21-4. External Reset Timing (RST) .............................................................................. 776
Figure 21-5. Power-On Reset Timing ..................................................................................... 776
Figure 21-6. Brown-Out Reset Timing .................................................................................... 776
Figure 21-7. Software Reset Timing ....................................................................................... 776
Figure 21-8. Watchdog Reset Timing ..................................................................................... 777
Figure 21-9. Hibernation Module Timing ................................................................................. 778
Figure 21-10. ADC Input Equivalency Diagram ......................................................................... 779
Figure 21-11. SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing
Measurement .................................................................................................... 780
Figure 21-12. SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer ................. 780
Figure 21-13. SSI Timing for SPI Frame Format (FRF=00), with SPH=1 ..................................... 781
Figure 21-14. I²C Timing ......................................................................................................... 782
Figure E-1. Stellaris LM3S5737 100-Pin LQFP Package Dimensions ..................................... 829
Figure E-2. 100-Pin LQFP Tray Dimensions .......................................................................... 831
Figure E-3. 100-Pin LQFP Tape and Reel Dimensions ........................................................... 832
November 17, 2011
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