LM3S5737 Datasheet, PDF (3/833 Pages) Texas Instruments – Stellaris® LM3S5737 Microcontroller

Stellaris® LM3S5737 Microcontroller
Table of Contents
Revision History ............................................................................................................................. 25
About This Document .................................................................................................................... 31
Audience .............................................................................................................................................. 31
About This Manual ................................................................................................................................ 31
Related Documents ............................................................................................................................... 31
Documentation Conventions .................................................................................................................. 32
1
1.1
1.2
1.3
1.4
1.4.1
1.4.2
1.4.3
1.4.4
1.4.5
1.4.6
1.4.7
1.4.8
Architectural Overview .......................................................................................... 34
Product Features .......................................................................................................... 34
Target Applications ........................................................................................................ 42
High-Level Block Diagram ............................................................................................. 43
Functional Overview ...................................................................................................... 45
ARM Cortex™-M3 ......................................................................................................... 45
Motor Control Peripherals .............................................................................................. 46
Analog Peripherals ........................................................................................................ 46
Serial Communications Peripherals ................................................................................ 47
System Peripherals ....................................................................................................... 48
Memory Peripherals ...................................................................................................... 49
Additional Features ....................................................................................................... 50
Hardware Details .......................................................................................................... 50
2
2.1
2.2
2.2.1
2.2.2
2.2.3
2.2.4
2.3
2.3.1
2.3.2
2.3.3
2.3.4
2.3.5
2.3.6
2.4
2.4.1
2.4.2
2.4.3
2.4.4
2.4.5
2.4.6
2.4.7
2.5
2.5.1
2.5.2
2.5.3
The Cortex-M3 Processor ...................................................................................... 51
Block Diagram .............................................................................................................. 52
Overview ...................................................................................................................... 53
System-Level Interface .................................................................................................. 53
Integrated Configurable Debug ...................................................................................... 53
Trace Port Interface Unit (TPIU) ..................................................................................... 54
Cortex-M3 System Component Details ........................................................................... 54
Programming Model ...................................................................................................... 55
Processor Mode and Privilege Levels for Software Execution ........................................... 55
Stacks .......................................................................................................................... 55
Register Map ................................................................................................................ 56
Register Descriptions .................................................................................................... 57
Exceptions and Interrupts .............................................................................................. 70
Data Types ................................................................................................................... 70
Memory Model .............................................................................................................. 70
Memory Regions, Types and Attributes ........................................................................... 72
Memory System Ordering of Memory Accesses .............................................................. 72
Behavior of Memory Accesses ....................................................................................... 72
Software Ordering of Memory Accesses ......................................................................... 73
Bit-Banding ................................................................................................................... 74
Data Storage ................................................................................................................ 76
Synchronization Primitives ............................................................................................. 77
Exception Model ........................................................................................................... 78
Exception States ........................................................................................................... 79
Exception Types ............................................................................................................ 79
Exception Handlers ....................................................................................................... 82
November 17, 2011
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