LM3S5737 Datasheet, PDF (499/833 Pages) Texas Instruments – Stellaris® LM3S5737 Microcontroller

Stellaris® LM3S5737 Microcontroller
13.3.7
13.3.8
13.3.9
13.4
■ If the FIFOs are disabled (have a depth of one location) and there is no data present in the
transmitters single location, the TXRIS bit is set. It is cleared by performing a single write to the
transmit FIFO, or by clearing the interrupt by writing a 1 to the TXIC bit.
Loopback Operation
The UART can be placed into an internal loopback mode for diagnostic or debug work. This is
accomplished by setting the LBE bit in the UARTCTL register (see page 513). In loopback mode,
data transmitted on UnTx is received on the UnRx input.
DMA Operation
The UART provides an interface connected to the μDMA controller. The DMA operation of the UART
is enabled through the UART DMA Control (UARTDMACTL) register. When DMA operation is
enabled, the UART will assert a DMA request on the receive or transmit channel when the associated
FIFO can transfer data. For the receive channel, a single transfer request is asserted whenever
there is any data in the receive FIFO. A burst transfer request is asserted whenever the amount of
data in the receive FIFO is at or above the FIFO trigger level. For the transmit channel, a single
transfer request is asserted whenever there is at least one empty location in the transmit FIFO. The
burst request is asserted whenever the transmit FIFO contains fewer characters than the FIFO
trigger level. The single and burst DMA transfer requests are handled automatically by the μDMA
controller depending how the DMA channel is configured.
To enable DMA operation for the receive channel, the RXDMAE bit of the DMA Control
(UARTDMACTL) register should be set. To enable DMA operation for the transmit channel, the
TXDMAE bit of UARTDMACTL should be set. The UART can also be configured to stop using DMA
for the receive channel if a receive error occurs. If the DMAERR bit of UARTDMACR is set, then
when a receive error occurs, the DMA receive requests will be automatically disabled. This error
condition can be cleared by clearing the UART error interrupt.
If DMA is enabled, then the μDMA controller will trigger an interrupt when a transfer is complete.
The interrupt will occur on the UART interrupt vector. Therefore, if interrupts are used for UART
operation and DMA is enabled, the UART interrupt handler must be designed to handle the μDMA
completion interrupt.
See “Micro Direct Memory Access (μDMA)” on page 287 for more details about programming the
μDMA controller.
IrDA SIR block
The IrDA SIR block contains an IrDA serial IR (SIR) protocol encoder/decoder. When enabled, the
SIR block uses the UnTx and UnRx pins for the SIR protocol, which should be connected to an IR
transceiver.
The SIR block can receive and transmit, but it is only half-duplex so it cannot do both at the same
time. Transmission must be stopped before data can be received. The IrDA SIR physical layer
specifies a minimum 10-ms delay between transmission and reception.
Initialization and Configuration
To use the UART, the peripheral clock must be enabled by setting the UART0 bit in the RCGC1
register.
This section discusses the steps that are required to use a UART module. For this example, the
UART clock is assumed to be 20 MHz and the desired UART configuration is:
■ 115200 baud rate
November 17, 2011
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