CC2510F16 Datasheet, PDF (65/244 Pages) Texas Instruments – Low-Power SoC (System-on-Chip) with MCU, Memory, 2.4 GHz RF Transceiver, and USB Controller

CC2510Fx / CC2511Fx
IRCON2 (0xE8) - CPU Interrupt Flag 5
Bit Field Name
7:5
Reset
0
R/W
R/W
Description
Not used
4 _WDTIF
0
3 _P1IF
0
2 _{UTX1IF /} 0
I2STXIF
1 _UTX0IF
0
0 _{P2IF /}
0
USBIF
R/W Watchdog timer interrupt flag
0 Interrupt not pending
1 Interrupt pending
R/W Port 1 interrupt flag.
0 Interrupt not pending
1 Interrupt pending
R/W USART1 TX interrupt flag / I²S TX interrupt flag
0 Interrupt not pending
1 Interrupt pending
R/W USART0 TX interrupt flag
0 Interrupt not pending
1 Interrupt pending
R/W Port2 interrupt flag / USB interrupt flag
0 Interrupt not pending
1 Interrupt pending
10.5.3 Interrupt Priority
The interrupts are grouped into six interrupt
priority groups and the priority for each group
is set by the registers IP0 and IP1. The
interrupt priority groups with assigned interrupt
sources are shown in Table 42. Each group is
assigned one of four priority levels, and by
default all six interrupt priority groups are
assign the lowest priority. In order to assign a
higher priority to an interrupt, i.e. to its interrupt
group, the corresponding bits in IP0 and IP1
must be set as shown in Table 41 on Page 66.
While an interrupt service request is in
progress, it cannot be interrupted by a lower or
same level interrupt. In the case when
interrupt requests of the same priority level are
received simultaneously, the polling sequence
shown in Table 43 is used to resolve the
priority of each requests.
IP1 (0xB9) - Interrupt Priority 1
Bit Field Name
7:6
Reset
0
R/W
R/W
Description
Not used
5 _{IP1_IPG5} 0
4 _{IP1_IPG4} 0
3 _{IP1_IPG3} 0
2 _{IP1_IPG2} 0
1 _{IP1_IPG1} 0
0 _{IP1_IPG0} 0
R/W Interrupt group 5, priority control bit 1, refer to Table 41
R/W Interrupt group 4, priority control bit 1, refer to Table 41
R/W Interrupt group 3, priority control bit 1, refer to Table 41
R/W Interrupt group 2, priority control bit 1, refer to Table 41
R/W Interrupt group 1, priority control bit 1, refer to Table 41
R/W Interrupt group 0, priority control bit 1, refer to Table 41
SWRS055F
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