CC2510F16 Datasheet, PDF (158/244 Pages) Texas Instruments – Low-Power SoC (System-on-Chip) with MCU, Memory, 2.4 GHz RF Transceiver, and USB Controller

CC2510Fx / CC2511Fx
U1UCR (0xFB) - USART 1 UART Control
Bit Field Name
7
FLUSH
6
FLOW
5
D9
4
BIT9
3
PARITY
2
SPB
1
STOP
0
START
Reset R/W Description
0
R0/ Flush unit. When set to 1, this event will immediately stop the current operation
W1 and return the unit to idle state.
This bit will be 0 when returning from PM2 and PM3
0
R/W UART 1 hardware flow control enable. Selects use of hardware flow control with
RTS and CTS pins
0 Flow control disabled
1 Flow control enabled
0
R/W UART 1 data bit 9 contents. This value is used when 9 bit transfer is enabled.
When parity is disabled the value written to D9 is transmitted as the 9^th bit when
BIT9=1.
If parity is enabled then this bit sets the parity level as follows.
0 Even parity
1 Odd parity
0
R/W UART 1 9-bit data enable
0 8 bits transfer
1 9 bits transfer (content of the 9^th bit is given by D9 and PARITY.)
0
R/W UART 1 parity enable
0 Parity disabled
1 Parity enabled
0
R/W UART 1 number of stop bits
0 1 stop bit
1 2 stop bits
1
R/W UART 1 stop bit level
0 Low stop bit
1 High stop bit
0
R/W UART 1 start bit level. The polarity of the idle line is assumed to be the opposite
of the selected start bit level.
0 Low start bit
1 High start bit
U1GCR (0xFC) - USART 1 Generic Control
Bit Field Name
Reset R/W Description
7
CPOL
0
R/W SPI 1 clock polarity
0 Negative clock polarity (SCK low when idle)
1 Positive clock polarity (SCK high when idle)
6
CPHA
0
R/W SPI 1 clock phase
0 Data centered on first edge of SCK period
1 Data centered on second edge of SCK period
5
ORDER
0
R/W Bit order for transfers
0 LSB first
1 MSB first
4:0 BAUD_E[4:0] 00000 R/W Baud rate exponent value. BAUD_E along with BAUD_M decides the UART 1
baud rate and the SPI 1 clock (SCK) frequency
SWRS055F
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