CC2510F16 Datasheet, PDF (101/244 Pages) Texas Instruments – Low-Power SoC (System-on-Chip) with MCU, Memory, 2.4 GHz RF Transceiver, and USB Controller

Byte/Word n+3
Byte/Word n+2
Byte/Word n+1
Byte/Word n
Byte/Word n-1
Byte/Word n-2
.
.
.
.
Byte/Word 3
Byte/Word 2
Byte/Word 1
Length = n
Byte/Word n+3
Byte/Word n+2
Byte/Word n+1
Byte/Word n
Byte/Word n-1
Byte/Word n-2
.
.
.
.
Byte/Word 3
Byte/Word 2
Byte/Word 1
Length = n
CC2510Fx / CC2511Fx
Byte/Word n+3
Byte/Word n+2
Byte/Word n+1
Byte/Word n
Byte/Word n-1
Byte/Word n-2
.
.
.
.
Byte/Word 3
Byte/Word 2
Byte/Word 1
Length = n
Byte/Word n+3
Byte/Word n+2
Byte/Word n+1
Byte/Word n
Byte/Word n-1
Byte/Word n-2
.
.
.
.
Byte/Word 3
Byte/Word 2
Byte/Word 1
Length = n
VLEN = 001
If n ≥ LEN, LEN bytes/words are
being transferred. The dotted line
shows the case where LEN = n + 1
VLEN = 010
VLEN = 011
VLEN = 100
Figure 27: Variable Length Transfer Count Options
12.5.2.4 Byte or Word
(WORDSIZE)
Transfers
Determines whether each transfer should be
8-bit (byte) or 16-bit (word).
12.5.2.5 Transfer Mode (TMODE)
The transfer mode determines how the DMA
channel behaves when transferring data.
There are four different transfer modes.
Single. On a trigger a single byte/word
transfer occurs and the DMA channel awaits
the next trigger. After completing the number
of transfers specified by the transfer count, the
CPU is notified (DMAIRQ.DMAIFn=1) and the
DMA channel is disarmed.
Block. On a trigger the number of byte/word
transfers specified by the transfer count is
performed as quickly as possible, after which
the CPU is notified (DMAIRQ.DMAIFn=1) and
the DMA channel is disarmed.
Repeated single. On a trigger a single
byte/word transfer occurs and the DMA
channel awaits the next trigger. After
completing the number of transfers specified
by the transfer count, the CPU is notified
(DMAIRQ.DMAIFn=1) and the DMA channel is
rearmed.
Repeated block. On a trigger the number of
byte/word transfers specified by the transfer
count is performed as quickly as possible,
after which the CPU is notified
(DMAIRQ.DMAIFn=1) and the DMA channel is
rearmed.
12.5.2.6 Trigger Event (TRIG)
A DMA trigger event will initiate a single
byte/word transfer, a block transfer, or
repeated versions of these. Each DMA
channel can be set up to sense on a single
trigger. The TRIG field in the configuration
determines which trigger the DMA channel is
to use. In addition to the configured trigger, a
DMA channel can always be triggered by
setting its designated DMAREQ.DMAREQn flag.
The DMA trigger sources are described in
Table 51 on Page 104.
12.5.2.7 Source and Destination Increment
(SRCINC and DESTINC)
When the DMA channel is armed or rearmed,
the source and destination addresses are
transferred to internal address pointers. These
pointers, and hence the source and
destination addresses, can be controlled to
increment, decrement, or not change between
byte/word transfers in order to give good
SWRS055F
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