CC2510F16 Datasheet, PDF(56/244 Page) Texas Instruments – Low-Power SoC (System-on-Chip) with MCU, Memory, 2.4 GHz RF Transceiver, and USB Controller

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CC2510F16 Datasheet, PDF (56/244 Pages) Texas Instruments – Low-Power SoC (System-on-Chip) with MCU, Memory, 2.4 GHz RF Transceiver, and USB Controller

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CC2510Fx / CC2511Fx

Mnemonic

Description

Program Branching

ACALL addr11

Absolute subroutine call

LCALL addr16

Long subroutine call

RET

Return from subroutine

RETI

Return from interrupt

AJMP addr11

Absolute jump

LJMP addr16

Long jump

SJMP rel

Short jump (relative address)

JMP @A+DPTR

Jump indirect relative to the DPTR

JZ rel

Jump if accumulator is zero

JNZ rel

Jump if accumulator is not zero

JC rel

Jump if carry flag is set to 1

JNC

Jump if carry flag is 0

JB bit,rel

Jump if direct bit is set to 1

JNB bit,rel

Jump if direct bit is 0

JBC bit,direct rel

Jump if direct bit is set to 1 and clear the bit to 0

CJNE A,direct rel

Compare direct byte to A and jump if not equal

CJNE A,#data rel

Compare immediate to A and jump if not equal

CJNE Rn,#data rel Compare immediate to reg. and jump if not equal

CJNE @Ri,#data rel Compare immediate to indirect and jump if not equal

DJNZ Rn,rel

Decrement register and jump if not zero

DJNZ direct,rel

Decrement direct byte and jump if not zero

NOP

No operation

Boolean Variable Operations

CLR C

Clear carry flag

CLR bit

Clear direct bit

SETB C

Set carry flag to 1

SETB bit

Set direct bit to 1

CPL C

Complement carry flag

CPL bit

Complement direct bit

ANL C,bit

AND direct bit to carry flag

ANL C,/bit

AND complement of direct bit to carry

ORL C,bit

OR direct bit to carry flag

ORL C,/bit

OR complement of direct bit to carry

MOV C,bit

Move direct bit to carry flag

MOV bit,C

Move carry flag to direct bit

Miscellaneous

TRAP

Set SW breakpoint in debug mode

Hex Opcode

xxx119

0x12

0x22

0x32

xxx019

0x02

0x80

0x73

0x60

0x70

0x40

0x50

0x20

0x30

0x10

0xB5

0xB4

0xB8 - 0xBF

0xB6 - 0xB7

0xD8 - 0xDF

0xD5

0x00

0xC3

0xC2

0xD3

0xD2

0xB3

0xB2

0x82

0xB0

0x72

0xA0

0xA2

0x92

0xA5

Table 37: Instruction Set Summary

Bytes Cycles

2

6

3

6

1

4

1

4

2

3

3

4

2

3

1

2

2

3

2

3

2

3

2

3

3

4

3

4

3

4

3

4

3

4

3

4

3

4

2

3

3

4

1

1

1

1

2

3

1

1

2

3

1

1

2

3

2

2

2

2

2

2

2

2

2

2

2

3

1

1

9 addr11[10:8] is mapped into bits 7:5 of the first instruction byte (i.e. the opcode). addr11[7:0] is

mapped into the second instruction byte)

SWRS055F

Page 56 of 241

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